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We are now looking for a AI Networking Chip Security Architect we are looking for an outstanding security architect with Networking focus to design, validate, and guide implementation of secure architecture of its core products. The candidate is expected to: define problems & deliver highly innovative solutions that lead to significant differentiation in the industry, translate customer needs into architectural, technical & strategic direction, and help to resolve objectives & long-range goals of the Security organization. Leaders in this role will help reduce risk, threats, and vulnerabilities and design new security technologies in our company networking products.
What youll be doing:
Own the security requirements for next gen networking chips in a verity of product lines.
Lead new security technologies definitions into the roadmap of our company Networking devices.
Work with technical and senior leadership staff to turn business directives into functional implementations.
Collaborate between multiple business units and development groups to ensure robust, secure service posture from design to implementation.
Provide hands-on security engineering expertise across a wide variety of platforms.
This role extends across multiple groups and excellent working knowledge in the following areas of expertise is necessary for success:
Chip Security Architecture
Embedded System Architecture and Design
Security around interconnects and protocols
Security Standards
Cryptography.

our companys Product Engineering group is looking for a well experienced Test architect to join our family and be a part of System Product Engineering. The System Product Engineering team is responsible to assure that our companys customers will get the best state of the art high-quality products.
The teams are involving and part of the full product lifecycle from architecture definition trough development till the product will be EOL (end of life). As part of the effort mentioned above, we are looking for an Electronic Engineer to join the System Design Testing Architecture team and lead Systems HW testability definition for our companys Networking systems.
What youll be doing:
Leading optimal products testing definitions includes: HW, SW, FW, Mechanical fixtures, and cables/harnesses for customized production testing set ups.
Making pitches in front of large audience a new product testing architecture, DFT and testing method while providing justifications for the testing concept.
Responsible for product testing maximum coverage, Testing specification documents and production test flow process for each system
Working with Companys engineering team during the developing process of the product from pre-design trough the design and influence on the product design from DFT design for testability aspects.
Supporting production ramp up and scalability, lead and fast responding time for ECR/ECO implications.
Examine New Technologies, testing capabilities and their implementation for the next generation products
Ensure testing set ups and coverage are met the DFT requirements and timetable
Lead DFT Risk assessment and drive mitigations to reduce the risks.
Working closely with variety of teams: R&D, HW and SW, Chip design, Operations, thermal, signal integrity, FW and SW, layout, and more
The position combines understanding of HW, SW, system manufacturing processes.

our companys Product Engineering group is looking for a well experienced Test architect to join our family and be a part of System Product Engineering. The System Product Engineering team is responsible to assure that our companys customers will get the best state of the art high-quality products using the below:
Development and deployment of automatic testers for our companys network business units (Computing network adapters and High-speed switch systems) including hardware and software
Analyzing and monitoring the manufacturing data and find / prevent quality issues based on big data using Machine learning, statistical tools, and AI (artificial intelligence)
Leading smooth production and capacity enlargement
Failure analysis of return material from customers to understand the reason of failures.
Validate the test performance and stability using QA (V&V validation and verification) methods
The teams are involving and part of the full product lifecycle from architecture definition trough development till the product will be EOL (end of life). As part of the effort mentioned above, we are looking for an Electronic Engineer to join the System Design Testing Architecture team and lead Systems HW testability definition for our company's Networking systems.
What youll be doing:
Leading optimal products testing definitions includes: HW, SW, FW, Mechanical fixtures, and cables/harnesses for customized production testing set ups.
Making pitches in front of large audience a new product testing architecture, DFT and testing method while providing justifications for the testing concept.
Responsible for product testing maximum coverage, Testing specification documents and production test flow process for each system
Working with Companys engineering team during the developing process of the product from pre-design trough the design and influence on the product design from DFT design for testability aspects.
Supporting production ramp up and scalability, lead and fast responding time for ECR/ECO implications.
Examine New Technologies, testing capabilities and their implementation for the next generation products
Ensure testing set ups and coverage are met the DFT requirements and timetable
Lead DFT Risk assessment and drive mitigations to reduce the risks.

our company's Imaging Radar group develops innovative high-performance Radar solutions for ADAS and Autonomous Driving markets. We are seeking an experienced System Architect to join us.
What will your job look like:
Lead End-to-end life cycle of the Radar System-on-Chip architecture definition and development.
Work in close collaboration with the various teams, including system, algo, design, verification, backend, firmware, package and post-silicon.
Provide architectural guidance and tradeoff recommendations throughout the whole design process from concept through production.
Responsible for 3rd party IP technical evaluation and selection.
Manage Interconnect, DSP and CPU definition and optimization.

our copmpany's Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of our company Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on performance, power and quality. Modern Clocking design needs to balance high frequency clocks with power, DFx, noise, circuit and physical design constraints.
What you will be doing:
Working on next generation of Networking Switch, NIC and SoC products.
Micro architect and design next generation clock topologies and modules.
ASIC Clock scheme definition.
Improve Power, Performance, and Area (PPA) of state-of-the-art company chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with Physical design and timing team to evaluate Clocking concerns and come up with solutions for supporting high speed Clocking.
Understand physical aspects of the chip and develop enhanced clock distribution techniques.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Support Post-Si debug, characterization and productization activities.

We are now looking for a Power Optimization and Analysis Engineer! our company prides ourselves on having energy-efficient products. We believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. As part of the u/arch team in the Switch group, you will be responsible for analyzing full chip and unit-level power data and driving the FE/BE ASIC teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our company's products become more energy efficient. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of our company Switches product line.
As a member of Switch u/arch Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for our company's next generation switches. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.
What You'll Be Doing:
Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
Develop and share best practices for performing pre-silicon power analysis.
Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
Select and run a wide variety of workloads for power analysis.
Prototype new architectural features in Verilog and power analysis.

We are looking for a Senior Chip Design Engineer, Formal Verification for our company's Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking Switch and GPU technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies that are in the heart of the AI revolution. Our team delivers world class Chips solutions for HPC, AI infrastructures, data-center, network, and storage markets. We micro-architect, verify, and deliver smart and high bandwidth multi port switches. our company has the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tape-outs. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our company's core technology.
You will take part in the AI revolution led by our company, working on cutting edge architecture.