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we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

Our Sat Connect IC business unit, a division of our Satellite Systems business is a leading provider of ASICs, software, multibeam electronically steered antennas, and complete systems for communication satellites, as well as ground and airborne terminals. Located in Israel, the UK, Bulgaria, and the US, we are a techno logy leader in satellite communication.

Job Description:

Be part of a dynamic and motivated modem VLSI design team. Take part in a complex SOC VLSI chip-design activities with major focus on advanced digital signal processing and modem subsystem development, covering architectural, front-end design, verification and physical-design aspects.

VLSI development of digital modules from concept to final implementation, meeting physical design entry requirements
Be part of a multi-team developing advanced signal processing cores and subsystem solution
In charge of adjusting, deploying and integrating the subsystem into company design environment

Required Senior Software Engineer, CPU, Cloud
About the job
In this role, you will work at the center of our most strategic infrastructure investments. You will join a high-impact team operating on the critical path of our hardware and software evolution, bridging the gap between compute infrastructure and the massive scale of our software stack. You will be responsible for defining the methods and technologies required to model, simulate, and analyze complex hardware systems, with a core focus on security, performance, and correctness analytics, ensuring the efficiency of our future compute platforms. As a software engineer in this group, you will act as an architect, designer, and coder taking ownership of your goal and working in close partnership with cross-functional teams to make it a reality.
You will be at the intersection of hardware design and software optimization for our next-generation high-performance compute cores. You will not just support existing infrastructure; but will be helping build the foundation of our future hardware. Because this work is on the "most critical path" for our future, you will have visibility into and influence over the core technology that powers our most intensive services. You will bridge the gap between silicon-level security research and massive-scale software implementation, working with experimental AI tools that are shaping how we verify and optimize future hardware. You will be building the foundation of our future hardware.
Responsibilities
Drive performance modeling and analysis for next-generation CPUs, while identifying architectural bottlenecks, ensure system correctness, and implement optimization strategies across hardware-software stack to maximize efficiency for compute workloads.
Design, develop, and maintain software modeling tools and simulation environments, leverage C++, Python, and AI-driven methodologies to perform studies and automate analytical workflows.
Conduct security analysis and threat modeling for hardware-software interfaces, while developing and implementing methodologies for detecting, mitigating, and analyzing side-channel and micro-architectural vulnerabilities, ensuring systems meet safety and privacy.
Explore, deploy, and scale experimental AI-driven tooling to automate verification workflows, enhance predictive modeling, and accelerate development cycles, actively contribute to expanding the team's suite of AI-assisted capabilities.
Provide technical leadership in system integration projects, guide cross-functional teams to resolve large-scale compute bottlenecks, influence architectural designs, and facilitate the successful deployment of hardware-software solutions.

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.
Your Impact:
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.
Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.
Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.
Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.
Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.
Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.
Help bridge between general DV methodologies and DFT-specific design and verification needs.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle-from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams.
This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions.
Key Responsibilities
DFT Architecture & Technical Leadership
Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies
Lead DFT planning, specification, and quality tracking across the project lifecycle
Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout
Execution Across the Full Lifecycle
Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels
Own end-to-end DFT activities from specification through silicon bring-up and production support
Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements
Methodology & Cross-Functional Impact
Develop and drive scalable DFT methodologies, flows, and automation frameworks
Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness
Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time.

Required Design Verification Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Verification Engineer, you will be a part of the Research and Development team to verify digital designs, develop constrained-random test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through corner-case testing.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/Universal Verification Methodology (UVM) or Specman to ensure effective test coverage.
Define and implement various coverage measures to capture stimulus and corner-case scenarios.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies.
This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.
Key Responsibilities
The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.
Key responsibilities include:
Develop and support physical design CAD flows using industry-standard EDA tools
Build automation infrastructure for implementation, analysis, reporting, and debug
Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification
Create scripts and utilities to improve productivity, quality of results, and flow robustness
Support and enhance flows based on Synopsys Fusion Compiler
Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity
Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues.

Are you passionate about systems programming at the intersection of hardware and software? Do you want your code to directly accelerate the world's largest AI training and inference workloads? The Elastic Fabric Adapter (EFA) Drivers team is looking for Software Development Engineers to design and implement the kernel drivers and userspace libraries that power high-performance networking for AWS's AI/ML and HPC infrastructure.

EFA is the custom network interface that enables thousands of GPUs and accelerators to communicate at near-wire-speed bandwidth and low latency, making it a critical enabler of both foundation model training and real-time inference serving at unprecedented scale. When customers train the next generation of large language models or serve billions of inference requests with tight latency SLAs on our EC2 P5, P6, or Trn instances, it's our driver stack that moves the data.

Key job responsibilities
- Design, develop, and optimize Linux kernel drivers (RDMA/EFA) and userspace provider libraries (rdma-core) that ship to millions of EC2 instances.
- Work directly with custom hardware - collaborate with chip designers to bring new silicon capabilities to life in software.
- Contribute to the upstream Linux kernel RDMA subsystem and rdma-core open-source project.
- Architect solutions for next-generation networking features: GPU-direct RDMA, adaptive routing, collective offloads, and multi-path transport.
- Build monitoring and automation tools to enhance driver testing for functionality, reliability, and performance.
- Own the full lifecycle: from initial hardware bring-up and feature enablement through testing, deployment, and production troubleshooting across the global AWS fleet.

we are disrupting data center processing with novel photonic engines solving the power and performance challenges. We are looking for an Embedded software engineer to join our dynamic team and play a key role in shaping the technological landscape of our organization. The successful candidate for this position has a track record of strength and aptitude relevant to the following areas:

we are looking for a Junior Hardware Engineer - Signal & Power Integrity.
You'll be joining our Signal & power Integrity team, which is at the center of the silicon development .
Our SIPI engineers deal with all system development aspects and deliver detailed specifications to other development team.
As SIPI engineer youll be required to design and analyze high speed analog/digital signals for networking products, with emphasis on high speed signal and power analysis of ASIC, Package and PCB. Model/simulate/characterize high speed systems, including high speed I/Os, chip packages, printed circuit boards, and system interconnects. Overcome the challenges of ultra-high data rate and cutting-edge technology. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

Lead the development of Sensing SDK, a core software toolkit that integrates a broad set of computer vision, audio, and voice libraries, along with AI operators. The SDK is specifically designed and optimized for latest NPUs and DSPs - NeuPro-M, NeuPro-Nano and SensPro2 - positioning it as a cornerstone of sensing and AI platform.

Key Responsibilities:

Lead and mentor a team of software engineers developing Sensing AI SDK. Architect and implement high-performance sensing SW components for AI, vision, Audio and voice optimized for vectorize SIMD execution. Collaborate with compiler and DevOps teams to ensure efficient development and deployment. Drive technical excellence through code reviews, design discussions, and continuous improvement. Own the SDK roadmap, planning, and delivery cycles. Engage with customers to enable successful pre-sale processes, support integration and gather feedback.

This is not a typical full-stack position. We're looking for an exceptional Staff / Principal Engineer who can own complex technical domains, shape system architecture, and lead end-to-end development while remaining 100% hands-on. You will report directly to the VP R&D, work closely with them on technical strategy and architecture, gradually take ownership of architectural responsibilities across the platform, and become one of the company's leading technical voices. Along the way you'll help mayors and other city leaders understand their residents and their city in more effective ways, improving the lives of millions of citizens around the world.

Key Responsibilities
Own complex product domains from architecture through production
Lead end-to-end feature development across frontend, backend, and cloud
Drive architectural decisions and technical direction across the platform
Design and build scalable distributed systems
Design and develop AI-powered capabilities as part of the core product
Work closely with the VP R&D on technical strategy and architecture
Mentor engineers through technical leadership (without people management)
Serve as one of the company's technical leaders, influencing engineering standards and long-term technical strategy

We are looking for a Principal Tech Lead to join our team.

So, what will you be doing all day?

As a Principal Tech Lead, your daily impact spans deep-tech execution, organizational mentorship, and bleeding-edge paradigm adoption:

Architectural Governance: Own the end-to-end design, scalability, and performance of complex backend distributed systems. Ensure architectures are resilient, modular, and optimized for intensive data workloads.
Agentic Engineering Innovation: Champion and embed Agentic SDLC paradigms, tools and solutions into the engineering lifecycle. Design frameworks that enable autonomous AI agents to build, test, and deploy features end-to-end, while enforcing rigorous quality gates and deterministic production guardrails.
Cross-Project Orchestration: Maintain an exceptionally large context window to actively guide and facilitate multiple highly technical streams and parallel projects simultaneously without losing focus or delivery speed.
Guild Leadership & Mentorship: Act as the primary technical sounding board for the engineering community. Lead backend guild sessions, introduce emerging technologies, and actively mentor senior and staff engineers to elevate the group's collective capabilities.
High-Velocity Execution: Lead by example. When taking on critical path, hands-on tasks, execute with unmatched speed and quality, demonstrating what peak operational efficiency looks like.

We are looking for a visionary engineering leader to architect and lead our quality engineering discipline into the AI era. You will own automation infrastructure, performance engineering, and all AI-driven quality initiatives - building and mentoring high-performing teams of engineers and architects who set the standard for how modern software is validated at scale.
This is not a maintenance role. You will disrupt legacy testing paradigms, champion agentic test generation, and embed AI-quality thinking into every stage of the SDLC - from the first commit to production monitoring. You will be the organizational bridge between engineering velocity and product reliability.
How will you make an impact?
AI Quality Strategy:
Define and lead all AI-augmented quality initiatives across the organization
Deploy LLM-powered test generation, triage, and root-cause analysis tooling
Build frameworks for validating AI/ML model outputs and non-deterministic behaviors
Evaluate and integrate emerging AI quality toolchains (GitHub Copilot, Claude, agents)
Champion responsible AI testing practices, coverage standards, and governance models
Automation Engineering:
Own the full automation strategy across UI, API, and integration layers
Architect scalable, maintainable test frameworks
Drive shift-left testing embedded in CI/CD pipelines (Jenkins, GitHub Actions)
Establish coverage KPIs, flakiness SLAs, and automation ROI metrics
Lead adoption of self-healing and AI-assisted test maintenance
Performance Engineering:
Lead performance and load testing strategy at enterprise scale
Define SLOs/SLAs and partner with SRE on reliability thresholds
Design continuous performance validation integrated into delivery pipelines
Drive root-cause analysis for regressions, bottlenecks, and latency spikes
Oversee toolchain including k6, JMeter, Gatling, and APM integrations
People & Org Leadership:
Lead and grow teams of automation engineers, performance engineers, and architects
Set technical direction, OKRs, and career ladders for the quality engineering org
Hire senior ICs and architect-level talent; build succession depth
Foster a culture of ownership, engineering craft, and continuous learning
Partner cross-functionally with Product, DevOps, and R&D leadership.

We are seeking an energetic and versatile Principal Software Engineer to join our elite team responsible for building our Identity Authentication platform. Driving the modernization of core, mission-critical authentication domains across our primary product, delivering massive impact at scale. In this role, you will be a core technical authority using AWS architecture, AWS CDK, and .NET to design, develop, test, secure, and deploy high throughput, production ready cloud services from planning to production. Working in full collaboration with security architects, product managers, and cross functional development teams, you will produce complex and advanced SaaS services that satisfy demanding scalability, security standards, and Non-Functional Requirements (NFRs).
Your Impact:
Lead the architectural design and system implementation of cloud-native, distributed microservices using AWS and .NET following secure-by-design principles.
Practice all aspects of the software development lifecycle within an agile, continuous-delivery environment.
Spearhead research into modern cybersecurity mechanisms, evaluate emerging tech stacks, and pioneer cut-edge solutions to solve complex platform bottlenecks.
Drive engineering excellence through code reviews, design discussions, and active coaching to uplevel engineers across the team.
Participate in continuous and iterative engineering cycles with a heavy focus on code quality, testability, supportability, performance, and cost optimization.