לוח משרות דרושים , לחיפוש זה נמצאו 500 משרות

21/07/2026

Physical Design Engineer, Sr Staff

Location: Hod Hasharon

Job Type: Full Time

We are seeking a seasoned Sr Staff Physical Design Engineer to provide technical leadership across full-chip and multi-die physical implementation on advanced TSMC FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.

What You'll Do
Architect and own the full-chip physical design strategy: floorplanning, power delivery network (PDN), clock architecture, PnR, and timing closure
Define and drive backend methodology standards across the team for advanced node tapeouts (N5/N4P/N3)
Lead critical timing closure efforts - MCMM, OCV, advanced ECO strategies, and cross-corner sign-off
Oversee and guide signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs
Architect and lead the development of scalable PD flow infrastructure using Python and TCL - including automated regression, sign-off reporting, and run management systems
Champion the adoption of Agentic AI in the design flow - define use cases, evaluate tools, prototype autonomous agents for floorplan exploration, timing closure, and ECO automation
Lead cross-functional design reviews with DFT, verification, analog, and process engineering teams
Interface with TSMC, EDA vendors (Synopsys, Cadence, Siemens), and internal research teams to evaluate and adopt new methodologies
Mentor and technically guide junior and mid-level PD engineers across the organization

Requirements:
10+ years of experience in digital Physical Design with a proven track record of tapeouts on FinFET nodes (N7 and below)
Deep expertise in full-chip and block-level floorplanning, clock architecture, STA, PnR, and physical sign-off
Expert proficiency in EDA tools: Synopsys ICC2/Fusion, Cadence Innovus, Calibre, PrimeTime, RedHawk / Voltus, StarRC / Quantus
Advanced Python and TCL scripting - ability to architect large-scale PD automation frameworks and flow infrastructure
Proven experience in flow development: designing, implementing, and owning end-to-end backend design flows at team or organization level
Demonstrated experience or vision for applying Agentic AI methodologies to EDA challenges - autonomous agents, AI-driven optimization, LLM-assisted debugging
Strong communication skills - ability to present methodology decisions, risk assessments, and tapeout readiness to senior management
Experience with power optimization (DVFS, multi-Vt, power domains, UPF/CPF)

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8747572

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

02/07/2026

Senior Analog Design Engineer, Cloud

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required Senior Analog Design Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Analog Design Engineer, you will design and integrate analog sub-systems. You will be responsible for ensuring the Analog Front-End (AFE) communicates flawlessly with the Digital Signal Processor (DSP), the package and silicon are a single electrical entity. Your work will bridge the analog and digital worlds to enable industry-leading performance.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Own the architecture and implementation of a major sub-component, such as the entire receiver AFE or the clocking/Phase-Locked Loop (PLL) distribution network.
Design the critical "suspension system" (e.g., Equalization/CTLE, ADC) that allows the digital core to function perfectly despite a noisy, high-loss channel.
Lead the definition and design of test chips to verify out novel topologies and circuit techniques in next-generation Gate-All-Around (GAA) nodes.
Collaborate with DSP, firmware, and system architects to define hardware/software partitioning and interface specifications.
Provide technical guidance and mentorship to engineers on the team.

Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
8 years of experience in Analog/Mixed-Signal design.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
Experience leading a block or sub-system tape-out for high-speed I/Os.
Experience demonstrating innovation in high-speed link design through patents or product releases.
Experience with package and PCB co-design and their impact on signal integrity.
Experience in system-level modeling and simulation using tools like Matlab or Python.
Knowledge of noise analysis, jitter decomposition, and adaptive loops.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8720648

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

01/07/2026

Senior SOC Quality and Reliability Engineer, Cloud

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required Senior SOC Quality and Reliability Engineer, Cloud
You will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the-art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. You will have an opportunity to create silicon and follow it into the field and back to drive improvements for the next-generations of chips.
As a part of this role, you will have an understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. You will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams within the larger organization.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Define and lead the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge/latch-up (ESD/LU), biased highly accelerated stress test (b/HAST), etc.) and conduct in-depth failure analysis to resolve quality issues.
Extract and analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical quality and reliability models (including early life failure (ELF), time-dependent dielectric breakdown (TDDB), and negative bias temperature instability (NBTI)) to predict device failure mechanisms and lifetime behaviors.

דרישות:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field, or equivalent practical experience.
10 years of experience in IC silicon quality or reliability.
Experience leading the product reliability life-cycle from post-tapeout through high-volume manufacturing.
Experience working with semiconductor Complementary Metal-Oxide-Semiconductor (CMOS) technology, device physics, and failure mechanisms.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related field.
Expertise in statistical data analysis using tools such as JMP, Python, or JSL.
Familiarity with Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) techniques.
Proven track record with silicon reliability on process nodes and advanced packaging technologies.
Deep knowledge of Design-for-Reliability (DfR) rules and implementation techn המשרה מיועדת לנשים ולגברים כאחד.

עדכון קורות החיים לפני שליחה

8718507

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

30/06/2026

DFT Engineer

Location: Tel Aviv-Yafo and Caesarea

Job Type: Full Time and Hybrid work

Required DFT Engineer
Job Description
Meet the Team
We are a leading Design for Test (DFT) group, delivering End-to-End solutions for our flagship products, including Silicon One!. Our chips are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance.
Our team operates in a hybrid model, with three days a week in the office in Azrieli Tower Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation!.
Your Impact:
Expand Your Scope- we provide engineers from different backgrounds the environment to master, standardize and evolve across different features.
Lead hands-on execution from pre-silicon design to silicon bring-up and production.
Collaborate with architects and verification teams to define the DFT roadmap for our next-gen Silicon One chips.

Requirements:
Minimum Qualifications
B.Sc. or M.Sc. in Electrical Engineering or a related field.
3+ years of experience with one or more of these features: MBIST, SCAN , ATPG, boundary scan technologies.
Strong communication and teamwork .
Preferred Qualifications
Experience across silicon product lifecycle- pre-silicon design to silicon bring-up and production.
Demonstrated ability to contribute to DFT methodologies for high-performance, AI-driven networking silicon.
Expertise in verification methodologies (e.g., UVM, SystemVerilog)
System-level understanding of complex SoC and networking silicon.
Experience with silicon debug, yield improvement, and test quality analysis.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8716862

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

01/07/2026

SoC Test Automation and Infrastructure Lead, Cloud

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required SoC Test Automation and Infrastructure Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Test (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips.
You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices, drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs
Responsibilities
Provide tools, set the environment and create automation to silicon engineering (SiEng) teams, collaborate with Test, Product, quality and reliability (Q&R) and system-level test (SLT) teams.
Create smooth and effective ways to manage silicon engineering (SiEng) datastream to and from suppliers and internally, between different platforms, while optimizing formats and datalogs, convert per need.
Verify test solutions on pre-silicon models (simulation or emulation) and support Automated Test Equipment (ATE) test development setup and environment.
Develop test method for ATE platforms.
Provide pre and post silicon dashboards and indicators that will reflect the status, demonstrate progress and point on the gaps.

Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in test or product engineering, with experience in infrastructure and automation and people management experience.
Experience in pre-silicon validation, test content generation, ATE program development, big data handling and post-silicon enabling from New Product Introduction through high-volume manufacturing.
Experience with ASIC test methodologies (mbist, atpg, dft serdes, sensors).
Experience with Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Masters in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
10 years of experience in test engineering, including product engineering.
Experience in ATE hardware design and proliferation: loadboards/probecards, handler kits, sockets, and thermal control solutions.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Inquisitive and motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8718703

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

24/06/2026

Senior/ Staff Package Design Engineer

Location: Merkaz

Job Type: Full Time

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world's largest AI clusters.
As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our companys products to operate reliably in the worlds most demanding AI and cloud environments.
Key Responsibilities
Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor technical reviews.

Requirements:
Basic Qualifications
5+ years of hands-on IC package design experience for high-performance semiconductor products, with full technical ownership from concept through tape-out
Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and hands-on experience designing complex packages (BGA, FCBGA, FCCSP)
Strong package integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership
Deep understanding of signal, power, and thermal integrity at the package level, with the ability to execute design tradeoffs based on analysis
Proven manufacturing and release experience, including running DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs
Preferred Qualifications
Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces
Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)
Experience supporting chiplet-based architectures and heterogeneous integration
Demonstrated track record of complete technical package ownership on high-volume products.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8709035

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

01/07/2026

Physical Designer Engineer, Cloud

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required Physical Designer Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
Responsibilities
Define and drive the implementation of physical design methodologies.
Take ownership of one or more physical design partitions or top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.

Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering or equivalent practical experience.
4 years of experience with System on a Chip (SoC) cycles.
Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.
Experience in high-performance, high-frequency, and low-power designs.
Preferred qualifications:
Masters degree in Electrical Engineering, or a related field.
Experience coding with System Verilog and scripting with Transaction Control Language (TCL).
Experience with Very Large Scale Integration (VLSI) design in SoC.
Experience with multiple-cycles of SoC in ASIC design.
Experience with layout verification and design rules.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8719218

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

21/07/2026

Senior Physical Design Engineer

Location: Rehovot

Job Type: Full Time

Be part of a dynamic and motivated multi-national Physical Design team, taking part in developing a state-of-the-art Satellite SoC through the full life cycle: design to production. The chips include complex digital and analog modules. Some of the products are part of the next generation radiation hardened satellite modems. You will have access to best-in-class EDA design tools and will be working in leading edge process technologies.

Responsibilities:
Physical implementation of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc).
Full block level timing closure and manufacturing checks signoff including power planning and analysis.
Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip level.
Insertion of DFT test structures and chip level integration, capture and simulation.
Jointly with management, build your career development and growth opportunities.

Requirements:
Bachelor of Science in Electrical Engineering, Computer Science, or related field from a major academic institute.
At least 8 years' experience as Physical Design Engineer.
Experience with COT/ASIC physical design flow covering: Synthesis, Floor-planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure, Physical Verification, Power Analysis, Formal Verification, DFT/DFM and ATPG insertion/pattern generation.
Deep sub-micron (28nm or below) process technologies
Industry standard design processes for deep sub-micron designs
Problem-solving and analytical skills
Practical use of scripting languages Tcl/Python/Perl etc.
Experience of at least one of the following EDA tool flows: Cadence or Synopsys.
Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow.
Managing/Interfacing to sub-contract design service providers.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8747727

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

24/06/2026

Staff/ Principal Physical Design Engineer - SoC EMIR Expert

Location: Tel Aviv-Yafo

Job Type: Full Time

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip
Collaborate closely with Physical Design team to insure a full power integrity
Be responsible on IR architecture for timing convergence
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)
Understand root-cause analysis for voltage drop violations and EM risks
Be responsible and go-to person for any IR related issues.

Requirements:
Basic Qualifications
Bachelor's or Master's degree in Electrical Engineering or a related technical field
10+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)
Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)
Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
Ability to define and own EMIR methodologies
Capability to identify issues early in the project lifecycle (preferably with experience in sub-N5 TSMC technologies)
Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM
Thermal analysis, self-heat and Statistical EM proficiency
Preferred Experience
Familiarity with thermal analysis tools and their interaction with electrical performance
Experience working with sign-off criteria and margins for high-volume production chips
Good understanding of timing and P&R
Good understanding of packaging, top metal layers, MIM capacitor usage, and power distribution
Understanding of ESD (including full CDM closure) and latch-up
Strong Reliability knowledge
Ability to write TCL scripts for STA and Fusion Compiler (FC).

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8708963

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

4 ימים

Physical Design Expert

Location: Haifa

Job Type: Full Time

Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Requirements:
BSc or MSc degree in Computer Engineering or Electrical Engineering.
8+ years experience in the Physical Design field.
Experience with high speed interfaces (DDR/PCIE) - an advantage.
Experience with advanced nodes (5nm and below) - an advantage.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
Building or maintaining implementation tools and flow - an advantage.
Experience in scripting languages like Tcl/Python/Perl/TCSH.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8760206

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

21/07/2026

ASIC Design Verification Engineer

Location: Hod Hasharon

Job Type: Full Time

As a Senior RTL Verification Engineer, you will lead the verification of complex subsystems and architectural features within a next-generation, high-performance RISC‑V Application Processor. You will work closely with architecture, design, modeling, software, validation, and implementation teams to ensure first-pass silicon success while meeting aggressive performance, power, and area (PPA) targets.

In this role, you will drive verification strategy, methodology, and execution from specification through tape-out, providing technical leadership in the definition of scalable verification environments, coverage closure plans, and debug methodologies. You will be expected to independently own large verification domains, influence design and architecture decisions, and mentor junior engineers.

The ideal candidate has extensive experience in CPU or SoC verification, with strong expertise in one or more of the following areas: RISC‑V architecture, CPU microarchitecture, MMU, memory hierarchy, cache coherence, interconnects, and micro-controller verification.

Responsibilities

Lead verification efforts for complex CPU and SoC subsystems from architecture definition through tape-out.

Define comprehensive verification strategies, test plans, coverage models, and closure criteria.

Architect, develop, and maintain advanced UVM-based verification environments and reusable verification components.

Drive verification execution, including stimulus development, functional coverage closure, assertions, regressions, and debug.

Collaborate closely with architecture and design teams to review specifications, identify ambiguities, and ensure verifiability.

Develop constrained-random, directed, and scenario-based tests to validate functional correctness and corner cases.

Drive root-cause analysis and resolution of complex design and verification issues.

Define and implement verification methodologies that improve scalability, quality, and productivity across the project.

Work with software, modeling, performance, and validation teams to develop system-level verification solutions.

Analyze verification metrics and risks, proactively driving closure plans to achieve project milestones.

Mentor junior verification engineers and contribute to the technical growth of the team.

Contribute to DV methodology discussions and influence verification best practices across the organization.

Requirements:
B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or related field.

5+ years of experience in RTL ASIC verification with demonstrated ownership of complex verification projects.

Strong knowledge of microprocessor architecture and verification methodologies.

Experience with one or more of the following:

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8747548

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

29/06/2026

Principal Software Development Engineer | Cortex Detection team (Backend)

Location: Tel Aviv-Yafo

Job Type: Full Time

Cortex is expanding. We combine the high energy of a startup with the massive resources of the worlds cybersecurity leader. We aren't just processing data; we are managing hundreds of petabytes of it, waiting Cortex for you to apply your "magic" to invent the next generation of threat detection. As a Principal Software Development Engineer, you will be a cornerstone of the Cortex Detection Backend team. This role is designed for a technical powerhouse who thrives in the "sweet spot" between high-level architectural strategy and hands-on execution. You will influence our product roadmap, mentor elite engineers, and build systems that protect thousands of the world's most sensitive organizations.
Key Responsibilities
Architect & Innovate: Design and build a new set of capabilities focused on Data Analytics and Threat Detection. You will solve cloud security challenges that have never been tackled before.
Scale Without Limits: Ensure our microservices architecture remains robust and resilient under massive loads, processing millions of events per second.
Technical Leadership: Act as a technical sounding board and mentor. You will guide design discussions, conduct deep-dive research, and foster a culture of engineering excellence.
Strategic Collaboration: Work closely with Product Management, R&D leaders, and Security Researchers to define requirements and turn ambiguous problems into elegant technical solutions.
Drive Execution: Take ownership of the software development life cycle, ensuring high-velocity delivery in a fast-paced Agile environment.

Requirements:
8+ years of experience in backend software engineering.
Deep proficiency in modern backend languages.
Extensive experience with Kubernetes (K8s) and microservices architecture.
Deep understanding of both SQL and NoSQL databases, including complex data modeling and performance optimization for massive datasets.
Expertise in scaling high-availability environments while championing a culture of engineering excellence and continuous operational improvement.
Experience leading technical projects or mentoring high-performing teams.
A track record of taking full ownership of production systems and solving high-stakes engineering bottlenecks.
B.Sc. in Computer Science, Software Engineering, or equivalent practical experience (e.g., alumni of elite technological military units).
Preferred Qualifications
Experience in high-scale SaaS or cybersecurity environments.
Deep proficiency in Go or Python.
Practical experience with GCP (Google Cloud Platform).

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8715111

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

05/07/2026

Senior Data Architect

Location: Tel Aviv-Yafo

Job Type: Full Time and Hybrid work

Were looking for a Senior Data & Analytics Architect to join our team and work directly with startup CTOs, engineering teams, and account teams. This is a hands-on, customer-facing architecture role where you will design and deliver production-grade data platforms on AWS.
The role is focused on turning real business problems into working systems, from early discovery and architecture design to supporting implementation. This is not a pure strategy or management role, its about making clear technical decisions and ensuring they hold up in production.
📍 Work location: hybrid from Tel Aviv
Key Responsibilities
Design and deliver end-to-end data platforms on AWS, covering ingestion, storage, processing, and serving layers, including Well-Architected reviews and contribution to SOWs and HLDs
Work directly with startup customers to understand requirements, challenge assumptions, and shape practical solutions
Lead technical discussions, workshops, architecture reviews, and POCs
Translate ideas and early concepts into clear architectures, including HLDs, SOWs, and implementation direction
Make and explain trade-offs across cost, performance, scalability, and complexity
Stay close to delivery, supporting teams to ensure solutions are implemented correctly
Collaborate with Data Engineers, DevOps, Solution Architects and Account Managers to move projects from concept to production
Contribute to internal standards, reusable patterns, and reference architectures
Operate in a fast-paced, project-based environment with multiple customer engagements
Stay up to date with modern Data Engineering and Analytics practices, and contribute to internal enablement, patterns, and knowledge sharing
Work in a customer-facing environment that includes occasional travel, both locally for meetings and events, and internationally around once per quarter

Requirements:
3+ years of hands-on experience with AWS, including solution design, migration, and production systems
2+ years in customer-facing technical roles, for example Cloud Architect, SRE, or Customer Engineer, working directly with stakeholders
Solid understanding of modern data architectures, including batch, streaming, and lakehouse patterns
Practical experience with core AWS data services, such as S3, Glue, Redshift, Kinesis or MSK, EMR, Athena, Lambda, and IAM
Familiarity with broader AWS infrastructure, including networking, IAM, and compute patterns
Experience working with real-time or near real-time data processing
Strong grasp of data modeling, pipelines, and storage optimization
Ability to reason about trade-offs, not just select tools
Ability to lead end-to-end technical engagements, from discovery through delivery
Comfort operating in fast-moving environments with ambiguous requirements
Clear communication skills, able to explain technical decisions to both technical and non-technical stakeholders
Strong communication skills in English. Spanish is a plus
Basic understanding of security and access control in AWS environments
Experience writing HLDs, SOWs, and supporting pre-sales engagements
Experience with ETL processes, data lakes, and pipelines
Nice to Have
Experience with Iceberg, dbt, or similar modern data tooling
Familiarity with Kubernetes, Docker, Terraform, and CI/CD pipelines
AWS certifications (Solutions Architect, Data Analytics, or similar)

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8723897

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

1 ימים

Senior storage infrastructure expert - 2412

Location: Merkaz

Job Type: Full Time and Public Service / Government Jobs

Are you a storage guru looking for your next challenge? Our storage infrastructure team is looking for a senior expert to lead the architecture, deployment, and optimization of our enterprise data storage environments within an innovative technological work environment.
In this role, you will tackle complex, large-scale technological projects, drive infrastructure automation, and ensure the resilience of our 24/7 mission-critical production systems. If you thrive in dynamic, high-impact environments, we want to hear from you!
עוד על התפקיד
Plan, architect, and deploy advanced, enterprise-grade arrays
Lead complex technological projects from design to implementation.
Maintain, optimize, and troubleshoot high-availability 24/7 production environments.
Drive automation processes and streamline operations by leveraging DevOps methodologies, advanced agents, and AI capabilities to enhance storage deployment, monitoring, visibility, control and support.

Requirements:
Storage expertise: 4+ years of hand-on experience managing centralized data storage systems in large-scale production environments (experience with NetApp, Dell, or Hitachi is major advantage).
Production resilience: proven experience supporting high-availability environments, including participation in an on-call rotation for non-standard hours/weekends when needed.
כישורים נדרשים
San networking: 4+ years of experience working with cisco storage switch infrastructures (MDS)
Backup Management: strong knowledge and experience managing enterprise backup systems, including media servers and working with veritas NetBackup.
Networking knowledge: good understanding of core networking concepts, protocols, and enterprise network environments.
Proficiency in writing python or bash scripts, or utilizing Ansible for storage automation.
Experience in project management (end-to-end planning and exection in enterprise environments).
Experience with Hybrid Cloud storage solutions or Object Storage (e.g., protocols).

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8763893

שירות זה פתוח ללקוחות VIP בלבד

שמך המלאמה השם שלך?

מייל

תיאור

שליחה

תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

האם תרצה להסיר את המשרה מרשימת

המשרות השמורות שלך?

כן לא

אירעה שגיאה בשליחת פרטיך למשרה

30/06/2026

Principal / Senior Software Engineer - CWP (Cortex Cloud)

Location: Tel Aviv-Yafo

Job Type: Full Time

We are seeking a high-caliber Principal or Senior Software Engineer to join our fast-paced Cloud Workload Protection (CWP) team within Cortex Cloud. In this pivotal role, you will lead the architecture and scaling of our core scanner, ensuring our cloud-native security solution delivers real-time vulnerability management and asset visibility at a massive scale.
As a technical visionary in our Tel Aviv office, you will drive end-to-end innovation for high-performance systems, championing engineering excellence and mentoring peers. This is a unique opportunity for a "can-do" engineer to build mission-critical security features that protect global cloud infrastructures from evolving threats.
Your Impact
Drive the Full Lifecycle: Lead the end-to-end development of features and core components across the entire software development life cycle-from initial design and development to testing, deployment, and maintenance.
Deliver High-Impact Solutions: Independently drive initiatives and collaborate with cross-functional teams to deliver critical features.
Elevate the Team: Play a crucial role in team-wide efforts by driving technical and architectural decisions, conducting design and code reviews, and raising the overall engineering bar.

Requirements:
8+/5+ years of experience working as a Software Developer
Development experience in Golang / Python / Java / C++ / C# or equivalent
BSc/MSc in Computer Science or equivalent military experience required
Hands-on with container runtimes (containerd, Docker, CRI, Podman) and OCI image internals
Linux systems knowledge (cgroups, namespaces, procfs, mounts).
Hands-on production experience with Kubernetes or container technologies
Experience in large organizations or innovative startups
Skilled at working with architects, QA, Frontend and other stakeholders to drive alignment and shared goals.
Open for learning, continuously seeks improvement, and encourages the same mindset in others.
Advantages: Knowledge in the cybersecurity space, cloud security.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8716890

שירות זה פתוח ללקוחות VIP בלבד