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we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we are now looking for an arch simulation manager to join our nvidia networking team! as a switch-arch simulation manager in nvidias networking business unit, you will lead a team of highly skilled hardware engineers responsible for verifying the next generation of nvidias cutting-edge switch products. this is a unique opportunity to make a real impact at the heart of nvidias ai and hpc revolution, while working in a fast-paced, innovative environment. you will be part of a passionate and experienced team using modern approaches to validate the performance requirements for the next generation of nvidia networking products. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of hardware Verification engineers focused on arch performance validation of complex digital designs.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of simulation deliverables to ensure high quality and timely tapeouts.

we are looking for individuals who thrive in a dynamic environment, and are not afraid to roll-up his their sleeves and get their hands dirty. we desire a self-starter, with great communication skills; as well as a leader, with a deep sense of commitment. you will be responsible for developing wafer forecasts, schedule generation and management, supporting cross-functional teams, and mitigating any programmatic risks. you will also review and improve processes, and handle prototype demand.
nvidia networking division is a leading supplier of innovative end-to-end nvlink, infiniband and ethernet connectivity solutions and services for servers and Storage. we offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. our products optimize data center performance, using nvidias ai solution and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of sectors, including high-performance computing, enterprise, data centers, cloud computing, Big Data, and web 2.0.
what you'll be doing:
you own silicon bring-up schedule from power on to production release
negotiate silicon and board demand with teams and drive a bottom-up forecast
oversee and manage chip and board allocations across the company
lead prototype chip delivery to internal customers
track and coordinate engineering deliverables, key milestones and qualification/validation tasks in the new product introduction phase
identify and mitigate risks to schedules and programs
communicate status to cross-functional teams as well as upper management
continuously evaluate internal tools and processes and drive fixes to improve productivity
create new and fix existing processes between different teams
drive implementation of sw tools for data analytics and process evaluation

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a SOC physical design engineer, you will collaborate with functional design, design for testing (dft), architecture, and packaging engineers. additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.the ai and infrastructure team is redefining whats possible. we empower customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our  users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
define and drive the implementation of physical design methodologies.
take ownership of one or more physical design partitions or top level.
drive to the closure of timing and power consumption of the design.
contribute to design methodology, libraries, and code review.
define the physical design related rule sets for the functional design engineers.

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip ( SOC ) group is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams.
what you'll be doing: implement chip level design through collaboration with cross-functional teams (functional design, dft, design verification, system verification, sta, and physical design).
be exposed and work on a variety of functional and structural challenges. including functional debug, physical design readiness, emulation, resolve design quality issues.
daily work involves aspects of chip level design, including partitioning, cdc, rdc, trial synthesis, design quality checks
taking part in flows development and deployment.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

we have been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world.
the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. thesystem -on-chip ( SOC ) group is seeking a top SOC Verification engineer to verify the design and implementation of the worlds leading networking socs. in this position, you will get the opportunity to craft complex networking chips and interact directly with architects, designers, and software engineers across sites. this is your chance to shape the future of computing with a world-class team! as an SOC Verification engineer, you will verify the design and implementation of our SOC technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches and nic SOC product lines. we are working closely with a wide range of aspects - chip design, dft, backend, verification and production testing. we are working on the most advanced technologies and complex products. our SOC solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the clock design elements, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our SOC verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

we are looking for an Electronic Engineer to join the system design testing architecture team and lead systems hw testability definition for nvidias networking systems.
what youll be doing:
leading optimal products testing definitions includes: hw, sw, fw, mechanical fixtures, and cables/harnesses for customized production testing set ups.
making pitches in front of large audience a new product testing architecture, dft and testing method while providing justifications for the testing concept.
responsible for product testing maximum coverage, testing specification documents and production TEST flow process for each system
working with companys engineering team during the developing process of the product from pre-design trough the design and influence on the product design from dft - design for testability aspects.
supporting production ramp up and scalability, lead and fast responding time for ecr/eco implications.
examine new technologies, testing capabilities and their implementation for the next generation products
ensure testing set ups and coverage are met the dft requirements and timetable
lead dft risk assessment and drive mitigations to reduce the risks.

we are now looking for a senior verification manager for our fc switch silicon team. as a fullchip verification manager in networking business unit, you'll lead a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a fc team, responsible to integrate and verify the switch at system level
lead and grow a team of fullchip Verification engineers
responsible to drive the fullchip verification execution, including staging plan of the projects and deliveries
provide technical guidance, mentoring, and support to engineers in the team.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw
dynamic verification environments planning for units infrastructures and system level
work with design/verification team which develops core units within the switch silicon.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

this senior role places you at the center of innovation, where you will have a direct impact on our business and technology by solving sophisticated technical challenges. its a unique opportunity to shape our technology and empower customers to build the supercomputers and ai fabrics of tomorrow.
what you'll be doing: lead the architectural design, development, and optimization of cutting-edge pcie firmware, using ai-driven modeling and insights to deliver exceptional performance.
serve as a trusted technical expert by investigating, debugging, and resolving challenging pcie firmware issues for our most important customers.
collaborate closely with our chip design, verification, software, and Architecture Engineers to find root causes and develop robust, long-term solutions.
champion the integration of ai-assisted diagnostics and generative ai tools across the entire development lifecycle to boost team productivity and innovation.
translate customer needs and field data into actionable feedback that directly shapes the future of our products.

come be part of our company, the industry leader in ai data centers. we are now innovating the future of data center, and defining the next generation of networking solutions. our team is dedicated to pushing boundaries and overcome the challenges involved in providing high performance data centers. as a network rdma algorithms architect, you'll contribute to our creative and cooperative setting, focusing on the connectx network adapter, spc-x end to end solution and more exciting technologies.
what you'll be doing:
conduct research and analysis on networking solution and end to end algorithms.
work with a creative and experienced team to outline the next generation of our rdma load balance and congestion control algorithms.
work on simulation environment and on real hw systems
engage with other research teams to develop proof of concepts using our technology.

we are building a high-impact team at the forefront of architectural innovation, and were looking for a senior nic system modeling & simulation engineer to be a key contributor. in this role, youll develop software-based functional models and simulators to explore, validate, and influence the architecture of our next-generation nics. you will work closely with architects and design teams, contributing to the design and evaluation of cutting-edge systems. this is a rare opportunity to shape architectural decisions from the ground up while working in a fast-paced, exploratory environment.
what youll be doing:
system -level modeling: architect and develop high-performance systemc models of hardware blocks and subsystems.
feature implementation: work autonomously to define, design, and implement modeling features.
cross-team collaboration: collaborate across architecture, design, and software teams to refine system -level behavior
ai-enhanced development: accelerate development by leveraging cutting-edge ai coding tools and frameworks.

We are looking for an experienced Software Architect with a strong SaaS background to lead architecture within the Assets (DAM) domain.

This role combines deep domain ownership with organization-wide architectural responsibility. You will be part of the Assets R&D group, reporting directly to the group manager, working closely with product and engineering teams, and at the same time a member of the Architecture Team, collaborating with other domain architects under the leadership of the Chief Architect.

You will define and drive the architectural vision of the Assets domain while ensuring alignment with broader system architecture, platform standards, and long-term technical strategy.

What Youll Do - Domain Architecture
Own and evolve the architectural vision and long-term roadmap for the Assets domain.
Define domain boundaries, core services, and major technical decisions.
Ensure the system supports scale, availability, multi-tenancy, security, compliance, and operational excellence.
Establish architectural standards and guardrails across teams.
Cross-Organization Leadership
Represent the Assets domain in the Architecture Team and contribute to company-wide architectural decisions.
Ensure alignment and interoperability with other domains.
Contribute to cross-cutting concerns such as reliability, security, observability, and cost efficiency.
Mentor senior engineers and elevate architectural practices within the group.
How Youll Work
Be embedded in the Assets group while aligned with the Architecture Team.
Engage early in strategic and planning discussions to shape direction.
Promote clear documentation of trade-offs and rationale.
Act as an enabler who helps teams move fast with strong architectural foundations.

In this role you'll own the design and delivery of Salesforce solutions end to end, combining architecture, development, AI capabilities, and business understanding This is a hands-on coding role . You'll design solutions and personally implement them using Apex, Lightning Web Components (LWC), APIs, and AI driven tools/processes The role also requires a strong understanding of end to end SaaS business flows (GTM, Sales, CS, Finance)

What will you do:

* Own Salesforce architecture and hands-on development across GTM and business systems
* Translate business needs into scalable solutions and implemented code
* Design and build across Sales Cloud, Service Cloud, Experience Cloud, CPQ
* Develop and maintain: Apex classes, triggers, test classes, Lightning Web Components (LWC) and Integrations (REST/SOAP APIs, async processing, events)
* Design and implement AI powered processes and automations (e.g., LLM-based workflows, enrichment, decisioning)
* Lead integrations with ERP, CPQ, marketing, and internal systems
* Make architecture decisions across data model, security, sharing, and performance
* Balance declarative vs. programmatic solutions
* Own code quality, testing, and performance optimization
* Lead code reviews and technical design
* Troubleshoot production issues and improve platform performance
* Work closely with Sales, CS, Finance, Marketing, RevOps, and MIS

About Us:
Cynet is a leader in threat detection and response, designed to simplify security for organizations of all sizes. Our mission is to empower lean security teams and their partners with an AI-powered, unified platform that autonomously detects, protects, and responds to threats - backed by 24×7 security experts. With a Partner First mindset , we focus on helping customers and partners stay protected, operate confidently, and achieve their goals. Our vision is to give every organization true cybersecurity peace of mind, providing fast, accurate protection without the noise or complexity.