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24/09/2026
Location: Haifa
Job Type: Full Time
As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing

Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness

Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust
Requirements:
Basic Qualifications
Bachelor's degree in Electrical Engineering or related technical field.
3+ years of hands-on experience in Physical Design at semiconductor companies.
Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing.
Experience working with advanced process technologies (7nm and below).
Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis.
Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks.

Preferred Qualifications
Experience with full-chip level implementation and integration.
Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon.
Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout.
Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus).
Background in high-speed interface designs or connectivity protocols.
This position is open to all candidates.
 
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24/09/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are hiring a Manager Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.

This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.

Key Responsibilities

RTL Design & Implementation
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality.

Cross-Functional Execution
Partner with architecture to translate specifications into implementation-ready microarchitecture.
Collaborate with verification on testplans, coverage closure, and bug triage.
Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.

Technical Leadership & Quality
Mentor junior engineers and contribute to design methodology, scripts, and best practices.
Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments.
Drive structured, data-driven design decisions in support of aggressive tapeout schedules.
Requirements:
Basic Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
5+ years of digital design experience, including at least one full chip from spec to tapeout.
Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
Hands-on experience with timing closure, CDC, lint, and low-power design techniques.
Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration.

Preferred Qualifications
MS or PhD in Electrical Engineering or Computer Engineering.
Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs.
Familiarity with formal verification, emulation, or assertion-based methodologies.
Background in advanced process nodes (7nm, 5nm, or below).
Strong debug skills across pre-silicon and post-silicon environments.
This position is open to all candidates.
 
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24/09/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Staff / Principal ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support.
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions.
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams.

Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient.
Apply design techniques to meet PPA (Power, Performance, Area) targets.
Contribute to design quality through verification and validation activities.

Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives.
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter.
Collaborate effectively across teams to ensure seamless integration.
Requirements:
Basic Qualifications
Bachelor's degree in Electrical Engineering or related technical field.
5+ years of experience in logic design at semiconductor companies.
Knowledge and experience in Verilog and/or SystemVerilog.
Excellent communication skills with ability to work effectively across teams.
Understanding of digital design principles and RTL coding best practices.

Preferred Qualifications
Master's degree in Electrical Engineering or related field.
Knowledge of DDR and PCIe protocols and implementation.
Understanding of power management techniques for low-power design.
Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis.
Proficiency in scripting languages such as Python or Perl.
Experience with high-speed serial interface designs or connectivity protocols.
This position is open to all candidates.
 
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28/09/2026
Location: More than one
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Perform advanced AI Static Timing Analysis (STA) for complex chiplet and full chip level.

AI use for timing optimization and data analysis in STA and PnR.

Running and build STA tools for anlyaze and debug timing.

Use traditional STA tools like Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.

Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.

Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering.

At least 5+ years of hands-on STA experience.

Experience in Prime Time and signoff methodologies.

A great teammate who thrives in a collaborative environment.

AI tools orientation or alternatively a desire to learn.


Ways to stand out from the crowd:

Agentic Frameworks.

AI prompting experience.

Experience in Linux environments.

TCL, Python, shell scripting abilities.

Experience with data collection and analysis.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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24/09/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams

Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities

Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration
Requirements:
Basic Qualifications
Bachelor's degree in Electrical Engineering or related technical field.
3+ years of experience in logic design at semiconductor companies.
Knowledge and experience in Verilog and/or SystemVerilog.
Excellent communication skills with ability to work effectively across teams.
Understanding of digital design principles and RTL coding best practices.

Preferred Qualifications
Master's degree in Electrical Engineering or related field.
Knowledge of DDR and PCIe protocols and implementation.
Understanding of power management techniques for low-power design.
Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis.
Proficiency in scripting languages such as Python or Perl.
Experience with high-speed serial interface designs or connectivity protocols.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Caesarea
Job Type: Full Time
Write and review micro-architecture specifications

Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements

Contribute to full chip integration, timing methodology, and analysis

Collaborate with verification engineers to resolve bugs and achieve coverage closure

Work with the physical design team to close timing and PnR issues

Support design methodology evolution and best practices

Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university

​Minimum of 8 years of proven experience in a relevant field

RTL design experience

Familiarity with UVM and functional verification methodologies
This position is open to all candidates.
 
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Location: Yokne'Am Illit
Job Type: Full Time
We are pioneering the future of medical diagnostics with our innovative capsule endoscopy solutions. Imagine a world where diagnosing gastrointestinal conditions is as simple as swallowing a pill which captures with imagers and different sensors the digestive system and transmit it in real time. Our cutting-edge technology not only makes this possible but also revolutionizes the patient experience, providing a non-invasive, accurate, and efficient diagnostic tool. We are seeking a dynamic and visionary Analog and RF engineer to join our dedicated team, driving the development and integration of our next-generation capsule endoscopy devices.
As a Senior Analog & RF Engineer specializing in capsule endoscopy development, you will play a key role in the design, development, and integration of the critical analog and RF communication path between the capsule, located inside the patients digestive system, and the external recorder worn by the patient.
You will be responsible for developing high-performance, low-power analog and RF solutions that enable reliable wireless communication, contributing directly to the performance and advancement of our next-generation medical devices.
In this critical role, you will collaborate closely with System Engineers, PCB design and Layout, Firmware Developers, Modem Algorithm Engineers, and Mechanical Design teams to develop and integrate advanced solutions across the system. You will work in a highly collaborative, open-minded environment that encourages new ideas, creativity, and innovation, contributing to cutting-edge medical technology that enhances patient care.
Primary responsibilities:
Own and drive the Analog & RF communication path from architecture definition through detailed design.
Work closely with leading semiconductor suppliers and technology partners on a system on Chip definition, development, and integration of custom IC/ASIC solutions, contributing to system architectural decisions and ensuring alignment with system-level requirements.
Research, evaluate, and define communication receiver and transmitter architectures, including Zero-IF, Low-IF/NZ-IF, Superheterodyne, and other relevant architectures, based on system requirements and product constraints.
Perform system-level RF and Analog analysis, including noise budget, link budget, dynamic range, sensitivity, linearity, distortion, interference, and overall communication-channel performance.
Develop simulation models and methodologies to evaluate communication-channel performance and validate architectural and design decisions prior to hardware implementation.
Design and specify the Analog transmitter and receiver signal paths, including filtering, amplification, gain stages, matching networks.
Analyse and optimize antenna design and RF performance, including antenna matching, efficiency, radiation characteristics, impedance, and interaction with the capsule and surrounding biological environment.
Drive a system on chip designs from proof-of-concept and laboratory prototypes into production-ready medical devices.
דרישות:
BSc \ MSc in Electrical Engineering.
7+ years of hands-on experience in very Low power Analog and RF engineering, preferably in wireless communication systems, RFICs, or mixed-signal systems; Familiarity with SoC/mixed-signal architecture, including considerations for integrating analog, RF, digital, and power-management functions.
Strong understanding of RF and analog communication architectures, including Zero-IF, Low-IF/NZ-IF, Superheterodyne, and related receiver/transmitter architectures; Proven experience with analog/RF transmitter and receiver design, including filters, amplifiers, LNAs, PAs, mixers, matching networks, and signal-conditioning circuits; Strong understanding of PCB-level RF implementation, including layout, grounding, shielding, power integrity, signal integrity, and RF isolation.
Preferred Qualifications:
Experience in writing design and technical specifications.#EN המשרה מיועדת לנשים ולגברים כאחד.
 
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27/09/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.

It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.

It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA.

It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.

It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development.

Key job responsibilities

- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).

- Verify IO sub-system features, including interconnect protocols and various accelerator engines.

- Develop and debug C embedded SW as part of hardware-software integration verification.

- Build and maintain UVM-based verification environments for various clusters and sub-systems.

- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.

- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).

- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.

- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.

- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.
Requirements:
Basic Qualifications
- 8+ years of experience in design verification of complex SoC or ASIC projects.
- Strong communication skills with the ability to collaborate across design, software, and physical design teams.
- Proven track record leading verification of IO sub-systems, interconnect fabrics, or system-level integration blocks.
- Deep expertise in UVM/SystemVerilog-based verification environments.
- Experience driving verification from product definition through post-tapeout silicon validation.
- Experience with performance verification methodologies alongside functional correctness.

Preferred Qualifications
- Strong knowledge of ARM interconnect protocols (AMBA CHI/ACE/AXI) and coherency verification.
- Experience with IO virtualization verification (SMMU, TLB, page table walks, memory attributes).
- C/C++ embedded software programming and firmware-level debug skills
- Experience with hardware-software co-verification.
- Familiarity with networking data paths and offload architectures.
- Understanding of physical design aspects and their impact on functional verification (e.g., clock domain crossings, power-aware verification).
This position is open to all candidates.
 
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Job Type: Full Time
As the Team Lead, you will manage a high-impact squad dedicated to ensuring our compliance with critical processes and data integrity. Your role is central to driving quality, scalability, and accountability in processes such as compliance audits, credit bureau furnishing, and legal automation. This is an exciting opportunity to work at the intersection of technology, compliance, and data. You will lead Backend Engineers and Data Engineers to build robust systems that power our regulatory functions. You will have the chance to shape the technical strategy and build the team (hiring and mentoring), while remaining hands-on with modern technologies.

Key Responsibilities:

Manage and mentor a dynamic team of 3 engineers (Backend & Data), fostering collaboration and professional growth. You will also be responsible for hiring and onboarding new talent to the team.

Architect scalable, high-performance systems that support compliance-critical operations. You will define the technical roadmap and drive modernization efforts.

Design and oversee both Backend infrastructure and Data Pipelines to ensure accurate, auditable, and scalable compliance processes.

Act as the single point of contact for legal and compliance stakeholders, handling and facilitating all technical aspects of audit requests (SOC, state, and other regulatory audits).

Collaborate with cross-functional teams, including other engineering teams, product managers, legal, and business stakeholders, to align technology and compliance goals.

Remain active in the codebase, ensuring high code quality and leading by example.
Requirements:
Requirements:
B.Sc. in Computer Science, Engineering, or a related field (or equivalent experience).
5 + years of experience in software development (Backend focused), with a strong emphasis on system architecture.
2+ years of experience leading engineering teams, mentoring developers, and managing end-to-end project lifecycles in production environments
Strong background in building large-scale, high-performance systems and designing distributed microservices.
Experience with data pipelines and big data infrastructure (familiarity with tools like Spark, Airflow, or Snowflake is a plus).
Hands-on experience with Java or Kotlin in production, and familiarity with Cloud technologies (AWS).
Ability to collaborate and communicate effectively across teams (Engineers, Product, Legal) and with senior leadership.
Passion for compliance, data accuracy, and impactful results. Solution-oriented mindset with a proactive approach to problem-solving.
Adaptability to thrive in a fast-paced, dynamic environment.
Proficiency in written and spoken English.
Experience with AI tools and a strong interest in continuously exploring and applying them in everyday work are highly valued.

Advantage:
Strong proficiency in Kotlin.
Experience with Event-Driven Architecture and Kafka.
Domain Expertise: Background in Fintech, Banking, or Regulation/Compliance environments.
Data Tools: Experience with specific data engineering tools like Snowflake, Spark, or DBT.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
Join a platform engineering team and provide hands-on technical leadership in evolving a Kubernetes-based platform for enterprise network applications, shaping how applications integrate with and operate across cloud, hybrid, edge, and customer-managed environments.

Define platform architecture, technical strategy, and multi-release roadmaps; translate product and operational needs into clear designs and implementation plans.
Design and evolve Kubernetes capabilities, including cluster lifecycle, controllers and reconciliation, custom resources, scheduling, networking, storage, service discovery, and upgrades.
Lead the design and development of shared platform services for connectivity, identity and access management, distributed data, observability, lifecycle automation, and administration.
Improve reliability and security through high-availability design, recovery, backup and restore, capacity planning, production debugging, threat modeling, and vulnerability remediation.
Prepare the platform for future AI workloads through workload isolation, resource governance, secure model serving, telemetry, and accelerator support.
Raise engineering standards through hands-on development, design and code reviews, automated testing, CI/CD, incident analysis, mentoring, and AI-assisted engineering workflows.
Requirements:
A related bachelors degree and 8+ years of relevant experience, or equivalent practical experience.
5+ years building, operating, or extending production Kubernetes platforms.
Deep Kubernetes knowledge and strong Go and/or Java development experience.
Proven technical leadership of complex, cross-team initiatives from architecture through production.
Strong engineering expertise across distributed systems, Linux, containers, networking, security, CI/CD, and production troubleshooting.
Hands-on experience with AI-assisted development tools and agentic engineering workflows.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo
Job Type: Full Time
we are In this role, you will translate complex business objectives into scalable technical implementations using Meta's suite of advertising APIs, measurement solutions, and data integration tools. You will partner closely with sales and client teams to design end-to-end solutions that drive measurable marketing outcomes, helping some of the world's largest advertisers unlock the full potential of Meta's platform at scale.
Solutions Architect - (12 Month Contract) Responsibilities
Serve as a technical subject matter expert on Meta's advertising platform, including APIs, measurement frameworks, and data integration solutions, for enterprise clients and partners
Design and recommend scalable technical architectures that align client business goals with Meta's marketing technology capabilities
Collaborate with sales teams to identify and develop new opportunities by diagnosing technical gaps and proposing solutions tailored to client needs
Guide clients through end-to-end implementation of advertising APIs, pixel and conversion tracking, and data connectivity solutions
Analyze complex client business challenges and propose solutions grounded in Meta's platform capabilities and industry best practices
Build and maintain cross-functional relationships with product, engineering, and partner teams to advocate for client needs and influence platform improvements
Develop and deliver technical presentations, solution blueprints, and documentation for audiences ranging from engineers to marketing executives
Prioritize and manage multiple client engagements simultaneously, aligning deliverables to short, mid, and long-term business goals
Provide technical guidance to peers and contribute to onboarding and knowledge-sharing practices within the solutions architecture team
Leverage AI-integrated workflows to accelerate solution design, documentation, and client analysis, sharing learnings to scale adoption across the team
Requirements:
2+ years of experience in a solutions architecture, technical consulting, sales engineering, or partner engineering role
2+ years of experience working with web or mobile technology stacks, including API development, integration, and troubleshooting
Experience communicating technical concepts and solution designs to both technical and non-technical stakeholders, including marketing and executive audiences
Experience with SQL scripting, querying, and working with data pipelines or analytics platforms
Experience managing and delivering technical solutions across multiple concurrent client or partner engagements
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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12/10/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We're looking for an exceptional AI Architect / Tech Lead (Hands-on) to help shape the future of our platform.
‍About the Role:
This is a highly technical, hands-on leadership role for someone who loves solving complex engineering challenges.
You'll lead the architecture and development of our AI initiatives while remaining deeply involved in coding, technical decision-making, and mentoring the engineering team.
If you're passionate about building AI-native products, designing scalable systems, and leveraging the latest AI technologies to accelerate development-you'll fit right in.
What You'll Do:
Design and lead the architecture of complex AI-powered features and services.
Build scalable Full Stack solutions using Node.js and React.
Develop AI-native products using modern LLM technologies.
Drive technical decisions, architecture, and engineering best practices.
Mentor developers through hands-on technical leadership.
Work closely with Product, Design, and Customer Success to deliver impactful solutions.
Explore and adopt the latest AI tools to improve both our product and development workflows.
Requirements:
7+ years of Full Stack development experience.
Strong hands-on experience with Node.js and React.
Proven experience designing complex system architectures.
Excellent knowledge of SQL and database design.
Strong experience with AWS services and cloud-native applications.
Deep understanding of modern software development processes and best practices.
Hands-on experience building products with LLMs, AI Agents, RAG, MCP, and modern AI development tools.
Experience using AI extensively as part of the software development lifecycle-not just for experimentation.
Excellent communication skills and the ability to lead technical initiatives while remaining hands-on.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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23/09/2026
Location: Petah Tikva
Job Type: Full Time
We are seeking a Senior Principal Software Architect to define and drive the long-term architectural vision for our Secrets Manager SaaS product. In this role, you will lead the design and evolution of our services, ensuring they meet the highest standards of scalability, security, resiliency, and operational excellence. As one of the organization's senior technical leaders, you will shape architecture across multiple product areas, influence strategic technology decisions, and partner with Engineering, Product Management, Security, and Architecture leadership to build a world-class Secrets Manager solution. You will establish architectural standards, mentor engineering teams and architects, and drive modernization initiatives that accelerate innovation while reducing technical debt. Additionally, you will drive the assimilation of AI tools and methodologies into the software development lifecycle to enhance R&D efficiency and developer productivity.
Requirements:
A minimum of 10 years of professional experience, with demonstrated expertise in SaaS-based software architecture.
A collaborative technical leader who develops those around them and works constructively with peer architects to advance shared architectural goals.
Strong track record of leading POCs and hands-on technical exploration to introduce new technologies and continuously advance the product architecture.
A proactive, results-driven mindset with strong decision-making skills that balance architectural excellence and business priorities.
Strong understanding of system integration design patterns, with the ability to anticipate, assess, and mitigate technical risks.
Hands-on experience with containerized environments (Kubernetes, Docker, EKS, ECS, etc.) and/or serverless technologies (e.g., AWS Lambda).
Excellent verbal and written communication skills, with full professional fluency in English.
Highly self-directed, with a strong commitment to quality, continuous improvement, and technical excellence.
A self-learner with a passion for exploring new technologies and sharing knowledge across the team.
What Will Set You Apart:
Proficiency in Go, Ruby, or Java.
Strong hands-on experience with AWS cloud services.
Deep understanding of security principles and best practices for building highly scalable systems.
In-depth knowledge of authentication and authorization protocols.
Previous experience as an R&D manager.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Ramat Gan
Job Type: Full Time
we are looking for a Infrastructure Tech Lead.
What You'll Do:
Ship features across the stack, back end and front end, in your first months to learn the product, the codebase and the teams
Lead architectural and infrastructure initiatives end to end, from design to production: modernizing our mature PHP monolith, into microservices architecture, converting background processing to (TypeScript/Python) serverless on AWS, improving observability, and scaling our analytics on ClickHouse
Make key technical decisions and set best practices: system design, data models, code quality and testing, and when to bring in new technologies
Shape our agentic SDLC: how we plan, build, review and test with AI coding agents, and the guardrails around it
Write and review critical code across the stack, front end included, and mentor engineers through design and code reviews
Share ownership of production, including the on-call rotation
Work closely with Product, team leads and engineers across R&D to turn business needs into sound technical plans
Requirements:
8+ years of hands-on software development, building and running web applications at scale
2+ years as a tech lead, architect or in a similar role, leading the design and delivery of cross-cutting projects
Strong experience with at least one backend language (PHP, TypeScript/Node.js, Python, Java, C# or similar)
Hands-on experience with an agentic SDLC: using AI coding agents (Claude Code, Codex, Cursor or similar) to plan, write, review and test code
Experience evolving a large legacy codebase: refactoring, upgrades and incremental migrations while the product keeps shipping
Deep experience with MySQL or another relational database, including data modeling and performance at scale
Hands-on experience with AWS
Hands-on experience with infrastructure as code (CloudFormation, Terraform, Pulumi or similar)
Excellent communication skills and the ability to work across teams and departments
Fluent English
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo
Job Type: Full Time
As a Senior SOC Engineer within Unit 42 at Palo Alto Networks, you will drive the creation, validation, and optimization of custom detection rules and automated playbooks across our global customer base. Acting as a trusted advisor, you will collaborate closely with clients to maximize their security posture using Cortex XSIAM and Unit 42 expertise. This highly analytical role leverages your deep understanding of detection lifecycles, proactive automation, and threat intelligence to secure enterprise environments. You will architect end-to-end security lifecycles that seamlessly connect data ingestion with high-fidelity detection engineering.
Key Responsibilities
Own the full lifecycle of custom detections and response automations, deploying them as high-fidelity Cortex XSIAM correlation rules and playbooks through a rigorous engineering process of development, testing, staging, and soft implementation.
Drive the continuous refinement of correlation rules to ensure strict standards for performance, accuracy, and operational relevance.
Translate Unit 42 threat intelligence research and emerging adversary TTPs into actionable, robust detection logic.
Champion proactive automation by engineering sophisticated playbooks to resolve emerging security challenges and optimize operational workflows ahead of demand.
Architect the end-to-end security lifecycle within Cortex XSIAM, seamlessly connecting data ingestion, high-fidelity detection engineering, and sophisticated response automation.
Requirements:
5+ years of hands-on experience in a Senior SOC, Detection Engineering, or Security Architecture role utilizing SIEMs, firewalls, EDR, sandboxes, and SOAR platforms in complex enterprise environments.
Proven mastery of the Detection Engineering lifecycle, including experience with rule testing frameworks, soft-deployment strategies, and continuous tuning.
Demonstrated experience reviewing and QA-ing detection logic written by others, with the ability to provide constructive optimization feedback.
Exceptional consultative and communication skills, with the confidence to guide enterprise customers through complex architectural and workflow decisions.
Proactive engineering mindset with a track record of designing complex automation playbooks (Cortex XSOAR or similar) based on anticipated threat vectors, not just reactive requests.
Strong background in incident response, threat hunting, and translating threat intelligence into actionable defense mechanisms.
Software development experience with a strong proficiency in Python for security automation and scripting.
Preferred Qualifications
Previous hands-on experience utilizing and optimizing Cortex XSIAM.
This position is open to all candidates.
 
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