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We are seeking a talented and highly motivated Software Engineer to join our Chip Design Technologies team, which delivers best-in-industry Design, Formal Verification (FV), and Design Verification (DV) solutions and methodologies. This position focuses on developing AI, Machine Learning (ML), and Large Language Models (LLMs) based solutions to enhance design and verification methods. Whether you have several years of experience in AI or are a seasoned expert, this role offers the chance to make a significant impact in a rapidly evolving field.

What you'll be doing:

Define and develop cutting-edge AI and LLM-based solutions, tailored to enhance and innovate design and verification processes.

Deeply understand existing design and verification workflows, identify opportunities for improvement, and implement customized solutions that drive efficiency and effectiveness.

Collaborate closely with designers and verification specialists, ensuring seamless integration of AI/ML solutions across multiple projects.

We are looking for talented engineers to help us develop a semiconductor platform based on revolutionary architecture.
Take part in the development of cutting-edge products within a disruptive system architecture. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. our Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.
We are looking for talented physical design implementation engineers to join our excellent Physical Design team, which develops our next generation of products for the cloud market.
Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macros and clusters level, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsis and Cadence.
* Engaged in defining implementation and signoff methodologies.
A day in the life
Your day will be filled with dynamic technical challenges that push the boundaries of semiconductor design. You'll collaborate with cross-functional teams, diving deep into intricate physical design processes, and translating complex architectural concepts into tangible technological solutions. Expect to engage in cutting-edge problem-solving that requires both creative thinking and precise technical execution.

From early micro-architecture, design and verification, to post silicon validation - the team is responsible for the chip across it's full life cycle.
Our chip is one of the most complex chips in the industry.

Required DFT Engineer, Nitro Team
Description
AWS Utility Computing (UC) provides product innovations from foundational services such as our Simple Storage Service (S3) and our Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWSs services and features apart in the industry. As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS. Within AWS UC, our Dedicated Cloud (ADC) roles engage with AWS customers who require specialized security solutions for their cloud services.
Join a groundbreaking semiconductor team where your expertise will directly power the world's largest cloud infrastructure. At Annapurna Labs, you'll be instrumental in developing next-generation chip technologies that transform how global businesses leverage computing power, working at the intersection of innovative design and cutting-edge technological advancement.
Key job responsibilities
* Develop comprehensive Design-for-Testability (DFT) strategies for next-generation semiconductor platforms
* Collaborate across multiple engineering domains to ensure robust chip design and verification
* Generate and optimize test patterns using advanced methodological approaches
* Conduct detailed logic design and verification processes
* Support chip bring-up and contribute to the entire device lifecycle from definition to mass production
A day in the life
Your day will be dynamic and collaborative, diving deep into semiconductor design challenges. You'll engage with multiple engineering teams, crafting sophisticated test strategies, developing intricate logic designs, and contributing to the entire chip development lifecycle. Expect to transition seamlessly between technical problem-solving, collaborative design sessions, and strategic planning.

Join our team in a pivotal role where you'll own the entire IP-level netlist generation and timing convergence journey from synthesis to sign-off.
You'll drive synthesis, UPF power intent, scan insertion, and external IP integration while architecting timing constraints for both standard and complex custom designs that ensure sign-off quality from day one.
Working at the intersection of multiple disciplines, you'll partner closely with RTL designers to deeply understand design intent and clock architecture, collaborate with CAD teams to shape and optimize cutting-edge flows, and team with Physical Design engineers to achieve flawless timing sign-off.
We're seeking an innovative thinker who brings fresh perspectives to timing analysis methodologies and proactively identifies and resolves timing challenges to eliminate pessimism and accelerate convergence, ultimately making their mark on next-generation chip design.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part in flows development.

DustPhotonics is developing a cutting-edge technology in Silicon Photonics which is revolutionizing connectivity and communication in data centers. Silicon photonics is becoming a standard technology used for high performance systems, solving challenges of performance, integration, power and cost. This technology is growing rapidly also in other markets such as Healthcare, LIDARs and other sensors. At DustPhotonics, we are looking to solve the difficult problems, in a smart and simple way, by thinking out of the box, leveraging the knowledge and know-how of the team members, and work as team to create Magic. Our Company culture is characterized by accountability for our ethics, for being fair to every employee, customer, supplier and partner. We believe we must work hard and have fun on the way to success. We welcome you to join our team - Apply for your next career opportunity with us! We are looking for a Silicon Engineering Manager Job description As the Silicon Engineering Manager you will be responsible for improving silicon-photonics yield and performance through data-driven analysis, cross-functional collaboration and proactive issue resolution. You will serve as the key interface between R&D, Process and Production teams, ensuring efficient data flow, rapid issue identification and continuous process improvement across wafer fabrication, device testing, and packaging stages.

Responsibilities:

* Perform silicon process and chip-level data analysis, establishing correlation between chip and wafer performance.
* Lead process debug and yield loss analysis at chip/wafer level, driving root cause investigations and corrective actions.
* Manage engineering approval forum to release production material.
* Collaborate closely with vendors to implement new product tests and resolve technical/process issues.
* Act as a key interface between design, testing, and production teams, ensuring alignment across the product lifecycle
* Oversee and coordinate the transfer of data related to silicon design, testing, fabrication, and characterization between Production and R&D departments.
* Develop and implement data management strategies to ensure data accuracy, security, and accessibility.
* Maintain proper documentation of data transfer protocols, version control, and data integrity checks.
* Support data analysis efforts to improve silicon performance, yield, and quality.
* Ensure compliance with company policies and industry standards related to data security and confidentiality.

Hiring Manager:
Arie Faitelson

our company's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets our company's standards of quality and reliability.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Design, develop, and maintain CAD tools and scripts to automate and streamline design tasks, verification processes, and data analysis.
Administer and optimize the front-end compute environment, ensuring reliability, performance, and scalability.
Provide technical support and training to Design and Verification teams on the use of CAD tools, scripts, and the compute environment.
Identify opportunities to enhance front-end development workflows, implement improvements, and document best practices.
Work closely with design, verification, and CAD teams to understand their needs, gather requirements, and deliver effective solutions.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:
You will be in charge of state of the art Design for Test/ATPG flows and implementation.
Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.
Inventing and maintaining automation flows that provide the short test time to production.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

we are a global leader in autonomous driving technologies and advanced driver-assistance systems (ADAS). Our cutting-edge solutions, including the EyeQ chip, our company SuperVision, our company Drive, and our company Chauffeur, leverage computer vision and machine learning to enhance vehicle safety and enable self-driving capabilities. Integrated into millions of vehicles worldwide, our technology is redefining the automotive industry and driving the evolution towards smarter, safer, and more autonomous mobility. We are seeking a skilled and driven Algorithm Team Lead to research, develop, and deploy state-of-the-art lidar based techniques that deliver world-class results, enabling the safe development of Autonomous Driving features and Advanced Driver Assistance Systems. ** This position requires on-site presence at our Jerusalem office one day per week.
What will your job look like:
As an Algorithm Team Lead, you will guide a team of talented developers to:
Design, develop, and implement lidar based algorithms in both C++ and python to solve complex problems
Collaborate with cross-functional teams to understand requirements and deliver robust solutions
Conduct research, evaluate existing models and techniques, and propose innovative approaches to improve algorithm performance and accuracy
Optimize existing algorithms for better performance and scalability.

we are a global leader in autonomous driving technologies and advanced driver-assistance systems (ADAS). Our cutting-edge solutions, including the EyeQ chip, our company SuperVision, our company Drive, and our company Chauffeur, leverage computer vision and machine learning to enhance vehicle safety and enable self-driving capabilities. Integrated into millions of vehicles worldwide, our technology is redefining the automotive industry and driving the evolution towards smarter, safer, and more autonomous mobility. In our group, we research, develop, and deploy state-of-the-art lidar based techniques to achieve world-class results, enabling the safe development of Autonomous Driving features and Advanced Driver Assistance Systems.
What will your job look like:
Research, design, develop, and implement lidar based algorithms in both Python and C++ for solving complex problems
Evaluate existing models and techniques, and propose innovative approaches to improve algorithm performance and accuracy
Examine your algorithms on large-scale real-world data from our data collection vehicles across the globe
Collaborate with cross-functional teams to understand requirements and develop solutions
Optimize existing algorithms to improve performance and scalability.

We are seeking a highly skilled and motivated architect to join our team. The ideal candidate will be responsible for leading quality activities across groups' solution-level features, ensuring the highest standards of quality are met. This role requires a proactive individual with excellent leadership and communication skills, capable of driving quality initiatives and fostering a quality-focused mindset within the organization.
Key Responsibilities:
Lead Quality Activities: Oversee and manage quality activities for cross-group solution-level features, ensuring alignment with overall quality goals.
Define E2E Scenarios: Define E2E scenarios for cross group projects and push for testable designs. Ensure E2E scenarios are covered by manual and automation by collaborating with the correct personas in the groups and the central QA.
Quality Point of Contact: Serve as the primary point of contact for quality-related matters concerning the unit or the cross-group feature.
Promote Quality Mindset: Work closely with the different personas in the groups to promote quality mindset, best practices, tools and product knowledge to improve the overall quality.
Strive for holistic solutions: Identify gaps that require a centralized solution and work with the centralized QA, PMO org and other solution quality leads to promote a holistic solution, enablement or processes .

We are seeking an experienced technical leader to head our collective communication library development team. This role involves leading a team of engineers in developing high-performance collective communication implementations for multi-NPU and multi-node AI workloads.
Key Responsibilities
Lead the design and development of collective communication primitives (All-Reduce, All-to-All, Gather/Scatter and etc)
Architect scalable communication protocols for multi-NPU and multi-node systems
Optimize communication performance for NPU architectures
Provide technical leadership to the team members in NPU programming, distributed systems, and communication protocols
Work with a success-driven worldwide international team (Network, NPU, QA, AI, DL/ML Framework)
Define project milestones, deliverables, and technical roadmaps
Ensure compatibility with major AI frameworks (PyTorch, TensorFlow, JAX).

We are seeking an Application Security Engineer to join our Cyber Team in our company. As an Application Security Engineer, you will be responsible for overall Application Security standards, guidelines, and requirements for different groups in our company. Your expertise in secure architecture, design, and SSDLC will play a crucial role in ensuring the security of our products and the protection of our sensitive financial data. This is a strategic position that offers an opportunity to shape and drive the security initiatives of our cutting-edge fintech solutions.
What youll do:
Review and approve secure architecture designs for new features and use-cases for our company customers, partners, integrators or in-house solutions, considering best practices, regulatory requirements and business objectives.
Collaborate with cross-functional teams (mainly R&D and DevOps/DevSecOps) to define security requirements and design robust security controls for systems, both on-prem and in the cloud.
Define CI/CD processes and gates, such as SAST, SCA, Secret scanning and image/containers scanning during CI and Runtime.
Provide technical guidance and expertise to internal teams in selecting and integrating in-house solutions or third-party vendors.
Stay up-to-date with the latest security technologies, threats, and trends, and provide recommendations for continuous improvement.
Serve as a subject matter expert on application security, providing guidance and mentorship to other teams in the company.
Assist in creating or researching for security solutions solving security challenges, both on-prem and in the cloud.