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Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Modeling of HW specification of new architecture and microarchitecture. Working closely with architect and microarchitecture on modeling the specification.

A leading semiconductor company, developing cutting-edge chips for accelerating analytical computing, is seeking a motivated Junior to Mid-Level Electrical Engineer to join our growing hardware team.
If you are passionate about electronics, eager to learn, and excited to work on cutting-edge technologies, this is the opportunity for you.
What You will be doing?
Design schematics for high-speed hardware boards. Support the full flow of PCB development
Collaborate with layout, manufacturing, and assembly teams
Perform lab testing, debugging, and system integration activities
Conduct soldering and rework on fine-pitch components as part of board bring-up
Document validation results and support design optimization for high-performance, small-footprint and reliability

Our New Product Introduction (NPI) team is growing, and We are now looking for a Chip Engineering Operations Program Manager! The Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the silicon schedule from bring-up to production release. We are looking for individuals who thrive in a dynamic environment, and are not afraid to roll-up his their sleeves and get their hands dirty. We desire a self-starter, with great communication skills; as well as a leader, with a deep sense of commitment. You will be responsible for developing wafer forecasts, schedule generation and management, supporting cross-functional teams, and mitigating any programmatic risks. You will also review and improve processes, and handle prototype demand.

What you'll be doing:

You own silicon bring-up schedule from power on to production release.

Negotiate silicon and board demand with teams and drive a bottom-up forecast.

Oversee and manage chip and board allocations across the company.

Lead prototype chip delivery to internal customers.

Track and coordinate engineering deliverables, key milestones and qualification/validation tasks in the new product introduction phase.

Identify and mitigate risks to schedules and programs.

Communicate status to cross-functional teams as well as upper management.

Continuously evaluate internal tools and processes and drive fixes to improve productivity.

Create new and fix existing processes between different teams.

Drive implementation of SW tools for data analytics and process evaluation.

As the Physical Design Group Leader, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Required Silicon Engineering Manager
Modiin, Israel Full-time
Responsibilities
Perform silicon process and chip-level data analysis, establishing correlation between chip and wafer performance.
Lead process debug and yield loss analysis at chip/wafer level, driving root cause investigations and corrective actions.
Manage engineering approval forum to release production material.
Collaborate closely with vendors to implement new product tests and resolve technical/process issues.
Act as a key interface between design, testing, and production teams, ensuring alignment across the product lifecycle
Oversee and coordinate the transfer of data related to silicon design, testing, fabrication, and characterization between Production and R&D departments.
Develop and implement data management strategies to ensure data accuracy, security and accessibility.
Maintain proper documentation of data transfer protocols, version control, and data integrity checks.
Support data analysis efforts to improve silicon performance, yield, and quality.
Ensure compliance with company policies and industry standards related to data security and confidentiality.

testing electro-optical and electrical chips and systems.
link-level performance characterization, verification, and debugging.
responsibility for complicated setups establishments, covering both optical and electrical components
characterizing optical and electrical performance using lab equipment and sw tools.
take an active part in silicon bring-up while managing e2e testing of the newest asics, with the objective of driving product to mass production with first-in-class performance.
characterizing products performance using lab equipment, such as oscilloscope, spectrum/network analyzer, pattern-generator, etc.
working in front of various TEST teams, with the responsibility of addressing issues and monitoring the TEST flows conducted by them

we are now looking for a versatile, fast learner, and highly motivated fe integration and eda tools engineer! as a member of our switch organization, you will be part of frontend integration and eda flows for a highperformance, lowpower switch chip. our fei team drives methodologies, automation, and quality for our frontend implementation and cd/ci, working closely with architecture, design, verification, and backend teams. this position offers you the opportunity to have real impact in a dynamic, technologyfocused company influencing future switch product lines. 
what you'll be doing:
driving frontend integration of major blocks in a pioneering ethernet switch asic, from rtl handoff through synthesis and signoff checks.
building, maintaining, and improving eda flows and methodologies for the switch org (lint, cdc/rdc, formal, synthesis/uls, fedct/fefc and related frontend signoff flows).
working closely with logic design and microarchitecture teams to define integration constraints, clocks/resets, interfaces, and quality targets.
partnering with dv, be, and cad/flow teams to ensure robust, scalable, and efficient frontend implementation across the project.
developing automation and infrastructure (scripts, regression flows, dashboards) to improve productivity, and debuggability.
debugging complex tool, flow, and design issues; driving rootcause analysis and longterm methodology improvements.

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we are looking for an Electronic Engineer to join the system design testing architecture team and lead systems hw testability definition for nvidias networking systems.
what youll be doing:
leading optimal products testing definitions includes: hw, sw, fw, mechanical fixtures, and cables/harnesses for customized production testing set ups.
making pitches in front of large audience a new product testing architecture, dft and testing method while providing justifications for the testing concept.
responsible for product testing maximum coverage, testing specification documents and production TEST flow process for each system
working with companys engineering team during the developing process of the product from pre-design trough the design and influence on the product design from dft - design for testability aspects.
supporting production ramp up and scalability, lead and fast responding time for ecr/eco implications.
examine new technologies, testing capabilities and their implementation for the next generation products
ensure testing set ups and coverage are met the dft requirements and timetable
lead dft risk assessment and drive mitigations to reduce the risks.

we are looking for best-in-class senior full-chip Verification engineer to join our networking silicon team. in this role, you will be responsible for the development and verification of our next-generation nics at the system level. you will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the worlds most advanced data centers, enjoy working in a meaningful, growing environment where you make a huge impact in a technology-focused company.
what youll be doing:
full-chip verification & execution: own complex system -level features by defining verification plans and driving the end-to-end execution.
system -level debug & analysis: gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance
cross-team collaboration: work closely with multiple teams within organizations such as architecture, u-arch, firmware and all units inside the nic
ai-enhanced development: accelerate development by leveraging cutting-edge ai coding tools and frameworks.

as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards. what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a silicon Validation engineer at our company cloud, you will play a pivotal role in the validation of our company's custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. with your expertise in post-silicon validation, you will be identifying and resolving issues before they impact our customers, ensuring a seamless and high performance cloud experience.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define, develop and execute post-silicon validation content on both pre-silicon setups and real silicon platforms in the lab.
drive silicon from being a chip towards becoming a product.
debug and investigate issues along cross-functional teams such as firmware, software, design, design verification, architecture and multiple production teams.
provide quality functional coverage for our company designs.
TEST development and automation, design, implement, and maintain validation tests using scripting and programming languages (e.g., Python, C / C ++) to verify smartnic functionality and performance.

our company networking system validation group is growing, and we are hiring a junior switch system Validation engineer. as a member of the team, you will take part in our core network projects which drive the growth of the company, tech and business wise. you'll gain networking and switch u-arch knowledge while helping validate, optimize, and debug devices in different areas like quality-of-service, performance, logic correctness, and ai features. 
you will work closely with logic design, circuit design, and architects to ensure successful product development with aggressive product cycles, in both pre and post silicon stages. 
you should have a good grasp of software development in different fields, such as Python scripting, Embedded software, and device firmware. it's important to have experience in a complex emulation environment and show a strong interest in creating, doing, and improving silicon validation plans. 

what you will be doing: 
work in a combined design and verification team specializing in switch full chip works
understand the switch architecture and build on  TEST plan accordingly 
develop full chip  TEST collaterals/suites, maintain regressions, debug failures and sign-off coverages 
maintain TEST suites to facility emulation and/or silicon platforms checkout as well