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we're seeking a highly skilled Physical Design Engineer specializing in EMIR & Power Integrity to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will execute the Electro-Migration and IR Drop (EMIR) analysis and sign-off from block level to full-chip, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. You will be responsible for validating power grid architectures to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Execute static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from the block level through to full-chip sign-off
Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Work with Physical Design teams to implement optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Collaborate closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Perform root-cause analysis for voltage drop violations and EM risks, proposing and implementing layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with strict foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

Nuvoton Israel is a leading supplier of SoCs, microcontrollers and security hardware solutions for tier-1 customers in the computing and server business. A self-contained design center, spanning from product management, system and chip architecture, through design, software development, system engineering and production. Our products combine unique sets control, management, and advanced security solutions, enabling our customers to establish differentiation in their end markets. We are looking for a Chip Design Verification engineer to join our Verification team! This is your opportunity to have an impact on the design of millions of computers sold worldwide each year by leading brands.
The role includes: - Building complex verification environments - Meeting the challenges presented by state-of-the-art design - Continues professional growth using the most advanced tools and methodologies - Use AI for improved productivity

We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
our Impact
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of exciting designs. resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flow development.

Power the Future with us! Atour company, we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery Storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. we offer amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. Are you passionate about designing high-performance power systems that move from concept to mass production? Join us and take a leading role in shaping our next-generation flagship products! What Youll Do:
* Lead the end-to-end development of advanced power electronics hardware - from architecture and schematic design through validation and mass production.
* Own complex board-level designs, driving performance, reliability, and cost optimization.
* Design, simulate, build, TEST, debug, and bring to life robust power solutions under real-world constraints.
* Collaborate in a multidisciplinary R&D environment alongside Mechanical, Software, system, and Certification teams.
* Influence product architecture and technical direction with hands-on engineering excellence.
* Ensure on-time delivery of high-quality, production-ready designs. Why Join Us?
* Work on impactful, market-leading products.
* Be part of a highly collaborative, multidisciplinary engineering culture.
* Take real ownership and influence technical decisions.
* See your designs transition from concept to millions of units in the field.
Country:
Israel
City:
Herzliya

our team in israel is looking for a dedicated chiplet sta owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing:
perform advanced static timing analysis (sta) at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.

we are looking for best-in-class sta physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you will be doing:
sta analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing eco generation for block level and full chip level.
taking part inflows development.

we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

we're seeking a visionary Physical Design Subsystem (Multiple IPs/Partitions) Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As the Physical Design Subsystem (Multiple IPs/Partitions) Lead you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SubSystem with your team for chips that drive the worlds largest AI clusters. You will lead the team and the transition from RTL to GDS, ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

Build and mentor a high-performing Partitions team , owning the end-to-end execution from Synthesis to Signoff
Take full ownership of Subsystem physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Lead and guide external contractors and global partners to ensure seamless execution and delivery
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our design-for- TEST engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for a dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

We are looking for a highly skilled Hardware Design Engineer to join our R&D team and take part in developing our ultra-deep-tech innovative products and solutions for wireless energy transfer systems for autonomous robotics. The team deals with multidisciplinary R&D tasks for developing in-house solutions and platforms. Come work with us in a dynamic working environment with high responsibility, joining us, youll have the chance to develop unique products from scratch to mass production.

Key Responsibilities:

Board design (schematic and PCB layout) - power, analog and digital.

Ownership of complex, multi-layer PCB development.

BoM optimization, component selection, and cost-reduction activities.

Supporting NPI processes and transition to manufacturing.

Hands-on debugging, testing, and lab verification of prototypes.

Cross-team collaboration: Hardware, Mechanics, Software, System, Validation, and Production.

We are looking for highly motivated engineers who love the challenges and the opportunity of a small company.
Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.

We are seeking a highly skilled Senior Communication PHY Algorithms Engineer.
This senior role is focused on the end-to-end research, design, and implementation of digital receivers for proprietary drone communication signals.
Responsibilities:
Mathematically characterize complex communication and signal detection problems. Analyze and assess design trade-offs based on both performance metrics and implementation complexity.
Develop and maintain simulations using MATLAB and Python.
Design digital receiver modules to be implemented either by FPGA of SW.
Implement features directly in SW or technically lead and verify the FPGA implementation efforts of the FPGA engineer.
Accompany the integration process of the feature until its end-to-end operation.

we are looking for a senior Verification engineer to join our fullchip switch silicon team. as a fullchip Verification engineer at our networking business unit, you'll join a group of passionate and talented engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a full chip verification team that is responsible to integrate and verify our switch products at system level
work closely with multiple teams within organizations such as architecture, u-arch, firmware and all units inside the switch
responsible to drive the fullchip verification execution, including staging plan of the projects and deliveries