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8750939

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08/07/2026

SoC Physical Design Engineer, Electrical Analysis

Location: Herzliya

Job Type: Full Time

Imagine what you could do here! In our company, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all our Hardware products. The same passion for innovation that goes into our products also applies to our practices, strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking our product! As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC.

As a member of our physical design team, you will be performing various electrical analyses at the block or chip level, including but not limited to Static/Dynamic IR, EM, Noise, and Signal EM.
You will work with the CAD/technology teams for flow bring-up and validation.
You will also collaborate with the implementation team during the entire chip design cycle to drive sign-off closure for tape-out.
You will handle schedules and support cross-functional engineering efforts.

Requirements:
Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience.
Knowledge of computer architecture, circuit design, and low-power techniques.

Preferred Qualifications
Experience with ASIC or AMS physical implementation and analysis flow.
Scripting skills to automate and debug verification flows for digital VLSI design.
Knowledge of industrial EDA backend verification tools including Redhawk, PrimeRail/Voltus and PrimeTime/Tempus.
Past experience with sign-off on successful chip tape-outs.
Circuit design background and SPICE experience.

This position is open to all candidates.

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8729021

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22/07/2026

Senior ASIC Design Infrastructure & Methodologies engineer

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

We're looking for a strong engineer who is passionate about creating design flows and automation flows that enhance both the productivity and quality of our design team. The ideal candidate brings proven expertise in RTL design and front-end methodologies while having good software skills and a drive for improving and automating flows. In this role, you'll collaborate closely with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce innovative automation solutions that streamline flows and elevate overall design quality.
Key job responsibilities

Core Responsibilities:
- Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards.
- Enhance and build design flows to boost the overall productivity of design teams.
- Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.

Requirements:
Basic Qualifications
- 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience.
- 7+ years of digital design in communication systems experience.
- 7+ years of full-custom analog or RF layout experience.
- 7+ years of wireless communications systems and implementation experience.
- 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience.
- 7+ years of verification in communication systems experience.
- 5+ years of UVM, C, System C, and scripting experience.

Preferred Qualifications
- Master's degree or Ph.D. degree in Electrical Engineering or related field.
- Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs.
- Experience with modern ASIC/FPGA design and verification tools.
- Experience with SOC bring-up and post-silicon validation.

This position is open to all candidates.

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8749892

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30/06/2026

SoC DFT Engineer, Cloud

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required SoC DFT Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
4 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
Experience with ASIC DFT synthesis, simulation, and verification flow.
Experience in DFT specification, definition, architecture, and insertion.

Preferred qualifications:
Master's degree in Electrical Engineering, or a related field.
Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
Experience in SoC cycles, silicon bringup, and silicon debug activities.
Experience in fault modeling.

This position is open to all candidates.

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8717493

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01/07/2026

Physical Design Lead, Cloud

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required Physical Design Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, youll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Lead physical design of complex SoC to tape-out while working with multiple team members.
Evaluate and develop physical design methodologies and decide on the SoC flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
Participate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.

Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience in silicon implementation and chip integration.
Experience in ASIC development teams.
Experience in managing physical design teams working on digital designs that produce and deliver silicon.
Preferred qualifications:
Experience in extraction of design parameters and analyzing data trends.
Experience and breadth in engineering across physical design, top-level implementation, GDS tape-out.
Experience in top-level floor planning, block integration, static timing analysis, and sign-off.
Understanding of circuit design, device physics, and deep sub-micron technology.
Knowledge of delivery of high complexity silicon in technology process nodes.
Ability to lead cross-functional teams.

This position is open to all candidates.

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8718525

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30/06/2026

Design Vision Lead, Cloud

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required Design Vision Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
Lead an edge AI IP design team across definition, implementation and deployment phases, while establishing IP development methodologies sharing unified blocks within the IP design team.
Author block-level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.

Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
15 years of experience with design from microarchitecture through implementation with Verilog/SystemVerilog language.
10 years of experience in managing teams and groups.
Experience in microarchitecture, design, verification, logic synthesis, and timing closure.
Experience working with system design principles for low latency, high throughput, security, and reliability.
Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
Preferred qualifications:
Master's degree or PhD in Engineering or equivalent practical experience.
Experience in micro-architecture and design of AI modules, optimizing their power, performance and area.
Experience in leading chip development projects and teams and execution.
Ability to motivate and focus on collaborative teams to achieve testing goals.

This position is open to all candidates.

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8717523

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30/06/2026

RTL Design Technical Lead, Servers, Cloud

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required RTL Design Technical Lead, Servers, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in RTL Design cycle from IP to SoC and from specification to production.
8 years of experience in Technical leadership.
Experience in the following areas: RTL Design, Design Quality checks, Physical Design aspects of RTL coding, and Power.
Preferred qualifications:
Experience with synthesis techniques to improve Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with Design For Test and its impact on Design and Physical Design.
Experience with a scripting language like Python or Perl.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, and ARM processors.
Knowledge of SOC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.

This position is open to all candidates.

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8717508

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לפני 11 שעות

DFT Verification Engineer

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

We are looking for a Chip Design Verification Engineer to develop the next generation of DFT technologies.

As a Chip Design Verification Engineer in the DFT team at NVIDIA, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.

As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.

Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

Requirements:
BSc. in Electrical Engineering or Computer engineering, or equivalent experience.

3+ years of practical verification experience.

Experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, Verilog, debug tools like Simvision/Debussy).

Experience with Specman is a plus.

Good understanding of RTL design (Verilog).

Strong debugging, problem solving and analytical skills.

Excellent communication and social skills.

Ability to work in a geographically diverse team environment.

Self motivated, independent and target oriented.

This position is open to all candidates.

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8765760

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01/07/2026

SoC / IP Architect

Location: Haifa

Job Type: Full Time

we are a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital world built for autonomous driving, cloud computing, and AI, we depend on computing systems daily. But how can we guarantee their safety, reliability and functionality? we are the first-ever company to provide visibility into next-gen chips while they are operating, based on the power of on-chip monitoring, machine learning, and data analytics.
Here at our company, you'll be part of a team that's unlocking deep insights to make electronics more reliable, efficient, and high-quality. We're trusted by industry leaders in data centers, automotive, communications, and consumer devices - we work with the world's largest and most notable companies in tech.
Why we are a great place to work:
Fast-paced and impactful: We're a mission-driven startup, so you'll tackle new challenges daily, wear many hats, and see your work directly influence the future of electronics.
Supportive company culture: Learn from the best. Our 200+ team members are experts in their field with a proven track record of success, and they're committed to fostering a collaborative and supportive work environment.
International presence: We're a multinational company with a diverse team across multiple locations around the globe. You'll collaborate on projects with international impact, gaining a global perspective of the tech industry.
Work with industry leaders: Our solutions are used by the biggest names in tech. You'll be part of the team creating the next generation of groundbreaking products.
Cutting-edge playground: We use the latest machine learning, platforms, and tools to push boundaries and achieve breakthroughs.
Real-world impact: Our work keeps data centers, cars, and other critical systems running smoothly. Your work will directly contribute to safer, more reliable electronics.
We are here for the win: Backed by industry veterans and leading investors, we offer a stable and secure work environment with plenty of room for growth.
we are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.

דרישות:
B.Sc. or M.Sc. in Electrical or Computer Engineering (or related field).
3+ years experience in SOC architectural roles
Technical knowledge: Strong understanding of SoC design flows, and system requirements.
Power and performance analysis: Ability to analyze and balance performance, power, and area trade-offs.
Strong system thinking - ability to move between micro-architecture depth and system-level abstraction.
Hardware and software collaboration: Proven experience working across hardware and software teams to achieve system goals.
Experience defining and documenting architecture specifications, interfaces, and integration flows.
Excellent communication and collaboration skills, with the ability to lead cross-functional discussions and influence stakeholders.
Experience as a Functional Safety manager, advantage
Proactive, curious, and detail-oriented - cap המשרה מיועדת לנשים ולגברים כאחד.

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8719344

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5 ימים

Electrical Validation & Embedded SW Engineer

Location: Haifa

Job Type: Full Time

Our Autonomous Driving group in Haifa is looking for an Electrical Validation & Embedded SW Engineer. This is an exciting opportunity to join a growing team of highly talented engineers, working on the worlds most advanced SoCs for ADAS and self-driving vehicles.
Electrical Validation engineers enable, debug, and validate high-speed interfaces - like LPDDR4/5/6, PCIe Gen4/5, CDPHY, and MPHY - using high-end Lab measurement equipment and advanced SW tools. This dynamic work environment requires interfacing with Silicon and hardware design engineers, Software developers, Signal Integrity, and System Validation teams. The proximity to Signal/Power integrity simulation activities - we are a single SIPI/EV team - is another powerful advantage, enabling joint simulation-measurement effort.
What will your job look like:
You will join a team of talented and experienced EV/SI/PI engineers with wide scope of responsibility, from Pre-Si SI/PI simulations to Post-Si Electrical validation and debug, covering all the high-speed analog interfaces of our EyeQ products.
Responsibilities include performing electrical spec compliance and system margin validation, interface optimization, statistical results analysis, validation flow definitions and automation, validation SW tools development, etc.
You will also deal with FW development, automation enabling, data post-processing and debug of high-speed interfaces, like LPDDR4/5, PCIe Gen4/5, and D/C/MPHY.

Requirements:
BSc or MSc in Electrical or Computer engineering
3+ years of hands-on experience in validation or HW/SW debug or embedded SW development.
Hands-on experience with test automation development or FW development or automated data analysis
Experience with advanced lab equipment (Scope, BERT, etc.) is strong advantage.
Experience in Signal/Power Integrity design - An advantage
Experience with analog circuits or PHY IP knowledge - An advantage
Strong sense of ownership, commitment, and responsibility
Good interpersonal communication skills.

This position is open to all candidates.

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8760195

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אירעה שגיאה בשליחת פרטיך למשרה

01/07/2026

Senior Physical Design Engineer

Location: Tel Aviv-Yafo

Job Type: Full Time

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues
Personal skills
Innovation, quick learning abilities
Team player
Commitment, full ownership of tasks
Excellent communication and presentation skills
Customer orientation
A strong sense of ownership.

Requirements:
8+ years of hands-on experience with ASIC physical design (RTL-to-GDS).
Proven experience taking multiple full-chip SoCs from RTL through tapeout.
Deep knowledge of Cadence and/or Synopsys backend flows (experience with both is a strong plus).
Strong understanding of PnR, timing closure, SI, power, DRC/LVS, and signoff.
Excellent debugging and problem-solving skills.
Strong scripting skills in TCL and Python.
Nice-to-have / Advantage
Experience with multiple power domains and low-power design techniques.
Background that spans both frontend (RTL) and backend.
Experience influencing or defining methodology across teams or projects.

This position is open to all candidates.

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8719368

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אירעה שגיאה בשליחת פרטיך למשרה

25/06/2026

Junior ASIC Design Engineer

Location: Tel Aviv-Yafo

Job Type: Full Time

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Junior ASIC Design Engineer, you won't just build chips - you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

Requirements:
Basic Qualifications
Education: Bachelors degree in Electrical Engineering, Computer Engineering, or a related technical field.
Experience: 0-2 years of experience in logic design (relevant internships, university labs, or hands-on academic projects are highly valued).
Technical Skills:
Foundational knowledge of Verilog and/or SystemVerilog.
Strong understanding of digital design principles and fundamental RTL coding concepts.
Soft Skills: Excellent communication skills with a strong motivation to learn, adapt, and collaborate effectively within cross-functional teams.
Preferred Qualifications
Master's degree in Electrical Engineering or related field.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8710942

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אירעה שגיאה בשליחת פרטיך למשרה

21/07/2026

Senior VLSI Architect High-Speed/Low-Power Interfaces

Location: Haifa

Job Type: Full Time

Be part of a team responsible for designing the next generation of mobile devices. The position includes responsibility for system analysis and HW architecture design for high-speed and low-power interfaces, networking protocols, storage processing, including acceleration of protocols reducing overall power consumption. The job requires collaboration with multiple engineering functions and teams in various geographical locations. It includes identifying system use, requirements definitions, understanding of industry specification for interfaces, operating in industry Standards committees, SW and HW interaction, performance analysis, and more.

Requirements:
Minimum Qualifications:

Knowledge and experience in high-speed interfaces, such as PCIe, Storage, Networking, Automotive interfaces

Several years of experience in ASIC design and development

Familiarity with VLSI and system-on-a-chip principles, operation, and internals

Preferred Qualifications:

Advantage to experience with ARM based SoC Real-time systems, SW architecture, and SW Drivers, Advantage to Linux and Android

Participation in standards organizations and contributing to published specifications

Good communication skills across engineering disciplines, both verbally and in writing in Hebrew and English

Education Requirements Required:

Bachelor's, Electrical Engineering, or equivalent experience

Preferred: Master's, Electrical Engineering, or equivalent experience

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8747544

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תודה על שיתוף הפעולה

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אירעה שגיאה בשליחת פרטיך למשרה

01/07/2026

Senior Physical Design Engineer

Location: Haifa

Job Type: Full Time

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues
Personal skills
Innovation, quick learning abilities
Team player
Commitment, full ownership of tasks
Excellent communication and presentation skills
Customer orientation
A strong sense of ownership.

Requirements:
8+ years of hands-on experience with ASIC physical design (RTL-to-GDS).
Proven experience taking multiple full-chip SoCs from RTL through tapeout.
Deep knowledge of Cadence and/or Synopsys backend flows (experience with both is a strong plus).
Strong understanding of PnR, timing closure, SI, power, DRC/LVS, and signoff.
Excellent debugging and problem-solving skills.
Strong scripting skills in TCL and Python.
Nice-to-have / Advantage
Experience with multiple power domains and low-power design techniques.
Background that spans both frontend (RTL) and backend.
Experience influencing or defining methodology across teams or projects.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8719352

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שליחה

תודה על שיתוף הפעולה

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אירעה שגיאה בשליחת פרטיך למשרה

01/07/2026

SoC Test Automation and Infrastructure Lead, Cloud

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required SoC Test Automation and Infrastructure Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Test (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips.
You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices, drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs
Responsibilities
Provide tools, set the environment and create automation to silicon engineering (SiEng) teams, collaborate with Test, Product, quality and reliability (Q&R) and system-level test (SLT) teams.
Create smooth and effective ways to manage silicon engineering (SiEng) datastream to and from suppliers and internally, between different platforms, while optimizing formats and datalogs, convert per need.
Verify test solutions on pre-silicon models (simulation or emulation) and support Automated Test Equipment (ATE) test development setup and environment.
Develop test method for ATE platforms.
Provide pre and post silicon dashboards and indicators that will reflect the status, demonstrate progress and point on the gaps.

Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in test or product engineering, with experience in infrastructure and automation and people management experience.
Experience in pre-silicon validation, test content generation, ATE program development, big data handling and post-silicon enabling from New Product Introduction through high-volume manufacturing.
Experience with ASIC test methodologies (mbist, atpg, dft serdes, sensors).
Experience with Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Masters in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
10 years of experience in test engineering, including product engineering.
Experience in ATE hardware design and proliferation: loadboards/probecards, handler kits, sockets, and thermal control solutions.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Inquisitive and motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8718703

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