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We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilities:
Join a team of VLSI frontend design engineers in Chain-Reactions projects.
Define, plan and implement our next chip in Chain-Reactions on-going product line and in a new product line of cryptography algorithms acceleration SoCs.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.

We are seeking an exceptional architect to join our Architecture team and help shape the future of quantum computing. As quantum computers near production scale, were uniquely positioned to define the system, the hardware, and software architecture that will power the next generation of computing.
In this role, you will be part of the architecture team, responsible for innovating, developing, demonstrating, and rapidly prototyping new hardware and end-to-end system concepts. This position requires strong hands-on expertise in hardware development, including PCB design, analog and power circuits, RTL, and control software. We are looking for someone with a strong ability to learn and adapt, a genuine passion for deep technical ownership and growth within the company. You will work closely with Product, R&D, and Research teams to turn ambitious ideas into working technical solutions. Youll work as a key contributor and technical expert, collaborating closely with all the company's technical disciplines.
Responsibilities:
Rapid prototyping of new hardware and technology concepts
PCB and analog circuit development
Measurements of analog and system performance to meet the product requirements
Evaluation of the prototype, including performance, compliance, implementation of risks, and potential mitigations.
Handover of the POC / prototyping results to R&D, including documentation and reference design.

The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Evaluate, analyze, implement, and integrate SRAMs, other memories (such as multiport register files), and custom circuits. Drive proper IP integration and margins with the physical design team.
Partner with foundries and IP providers, as well as internal technology, physical design, and architecture teams, to optimize products for PPA, schedule, and reliability in advanced CMOS nodes.
Drive and support test chip design, execution, and validation of critical circuit IPs.
Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
Drive development of a leading edge technology platform for custom, high performance ASICs and SoCs, from design through manufacturing, packaging, and test.

As a member of our physical design team, you will be performing various electrical analyses at the block or chip level, including but not limited to Static/Dynamic IR, EM, Noise, and Signal EM.
You will work with the CAD/technology teams for flow bring-up and validation.
You will also collaborate with the implementation team during the entire chip design cycle to drive sign-off closure for tape-out.
You will handle schedules and support cross-functional engineering efforts.

We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.
Taking part in flows development and deployment.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design & Power Methodology Team Manager within the Server Chip Design team, you will be responsible of managing and leading design and power methodologies from IP to SoC, pre and post silicon. You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
You will work closely with CAD vendors and internal teams to develop lead design and power methodology and execution.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead flow and methodology development and assimilation across multiple groups. Work closely with CAD tool providers as well as internal CAD teams.
Plan, execute, track progress, assure quality, and report status.
Work closely with internal customers and support multiple activities and deliverables.
Drive design methodologies such as design construction, CDC, RDC, SDC. Drive power at: IP and SoC RTL/Gate Level Optimization, estimation, correlation.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Your Impact:
Write and review micro-architecture specifications.
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements.
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure.
Work with the physical design team to close timing and PnR issues.
Support design methodology evolution and best practices.
Perform debug, root-cause analysis, and post-silicon validation in the lab.

We are looking for a phenomenal engineer to join the chip simulation team for networking chips and GPUs. This simulation platform enables our engineers across firmware, SDK, and OS domains to develop and test their code without relying on physical hardware. If you're a creative, self-driven engineer passionate about systems-level design and eager to build technology that empowers internal teams, we want to hear from you.

What Youll Be Doing:

Develop and maintain simulation infrastructure components for different simulation teams (GPUs, switches, NVLink, Ethernet, PHY) of our high-performance networking chips.

Define, implement, and validate simulations of core infra features, improve performance, maintain multi processes and multi-threaded IPC mechanisms (sockets, queues etc.), define architecture and the building blocks of the simulation.

Own, extend and optimize all the CI/CD of the simulation team, starting from servers installation to adding and maintaining various Jenkins jobs that help developer and improve their life.

Collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex behaviour in software.

Support internal users by debugging simulation flows and collaborating on bug resolution.

Take part in future-facing innovation by enabling simulation for next-generation devices and features.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

You will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.

We are now looking for a best-in-class Verification Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer in our GPU-Networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry - our GPU Super-Chip.

What youll be doing:

Work in a DV (Design Verification) team that has a global responsibility over deliverable units and clusters to the silicon GPU.

Integrations and Full-Chip models.

Verification of chip blocks/entities according to specifications under challenging constraints.

Ramp-up and run DV tasks on emulation platform.

Join our advanced packaging team to define and develop cutting-edge semiconductor package solutions for automotive-grade digital and RF System-on-Chip (SoC) products.
Youll collaborate with internal teams and external OSATs to deliver high-performance, manufacturable, and reliable packages that meet stringent automotive standards.
What will your job look like:
Define and specify advanced package architectures for digital SoCs and RF ICs in automotive applications.
Perform substrate design for flip-chip BGA (FC-BGA) packages, including stack-up, routing, and ball-out optimizations.
Evaluate and select substrate technologies, materials, and package solutions based on performance, cost, and reliability.
Collaborate with OSATs to define and validate assembly materials and process flows.
Work closely with internal teams such as Backend, SIPI, Product Engineering, and Quality & Reliability to ensure seamless integration.
Monitor yield, quality, and manufacturability across package development and production stages.
Support DFM reviews and ensure compliance with automotive standards and customer requirements

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

our company's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets our company's standards of quality and reliability.
As a Silicon Validation Engineer at our company Cloud, you will play a pivotal role in the validation of our company's custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. With your expertise in post-silicon validation, you will be identifying and resolving issues before they impact our customers, ensuring a seamless and high-performance cloud experience.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define, develop and execute post-silicon validation content on both pre-silicon setups and real silicon platforms in the lab.
Drive silicon from being a chip towards becoming a product.
Debug and investigate issues along cross-functional teams such as Firmware, Software, Design, Design Verification, Architecture and multiple production teams.
Provide a quality functional coverage for our company designs.

Do you want to help accelerate the networking solution across NVIDIA's product portfolio? NVIDIA Co-packaged silicon-photonics group seeks a dedicated R&D system engineer to join our silicon-photonics testing platforms team. We seek a skilled and experienced systems engineer to join our team.

The ideal candidate will have experience in these topics: high-speed testing of fiber-optic modules for telecom/datacom, lasers, and post-silicon verification. In this role, you will lead the design, Integration, and deployment of electro-optical testing platforms for SiPh. You will work closely with the R&D teams, internal verification teams, architects, FW developers, market-leading subcontractors, and other stakeholders to design systems. This role requires hands-on experience and a deep system-level multidisciplinary understanding of high-speed transceivers, as well as excellent integration, problem-solving skills, and strong communication abilities.

What youll be doing:

You will lead the design of testing setups for bringing up and testing the new SiPh transceiver chips.

Provide technical support and assistance to manufacturers of silicon photonics testing platforms.

Troubleshoot and diagnose technical issues related to equipment, processes, and software.

Document experimental procedures, results, and findings accurately and comprehensively.

Collaborate with cross-functional teams, including engineering, product development, and manufacturing, to resolve complex technical issues and implement system upgrades or modifications.