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we are looking for a senior software engineer to join our team developing software solutions to control nvidia hw in Python on Linux for various internal engineering groups, including chip designers, algorithm engineers, phy characterization engineers, optics engineers, and other r&d teams. our work includes building and maintaining a framework, as well as developing gui tools that support complex engineering workflows. this role combines advanced software engineering with a hardware-oriented perspective - the ideal candidate should have both the interest and background in areas such as hardware, Linux systems, and low-level drivers.
collaborate with the development team to improve existing framework and tools, suggest creative solutions, and develop new projects.
in our group, software engineers are responsible for the full lifecycle of solutions - from defining requirements and designing architectures to implementation, integration, and delivery. this approach allows every team member to grow professionally, develop a broad skills, and unlock their full potential.
what youll be doing:
design, develop, and maintain Python -based software solutions (framework, internal tools, gui applications with pyqt).
collaborate with internal customers - including chip designers, algorithm engineers, optics engineers, phy characterization engineers, and other r&d teams - to understand requirements and translate them into robust solutions.
take full ownership of projects: define the solution, design the architecture, implement, integrate, and support production-ready tools.
extend existing framework and tools, while also designing and implementing new ones from scratch.
work within Linux environments, integrating software with hardware interfaces, drivers, and engineering workflows.
apply oop principles and design patterns to build scalable, maintainable software architectures.

Were looking for a talented and driven Integration Team Lead to join our System Engineering group. In this role, youll lead the integration team, working closely with system engineers, V&V, and other R&D functions to bring cutting-edge technologies into reality.
Responsibilities
Lead and manage the integration team, including task planning, setting priorities and mentoring team members
Be the technical focal point for integration-related activities
Oversee system testing and manage the handover process from Integration to V&V
Lead system bring up activities
Responsible for troubleshooting efforts and resolving problems in a timely manner
Maintain a broad understanding of the entire system and stay up to date with the latest version
Lead by example, motivate, empower and develop team members to reach their full potential
Establish strong working relationships with System Engineering and V&V teams to ensure high-quality delivery
Collaborate closely with multiple cross-functional teams across the organization

detailed design of the electrical schematics in the product, board design and components selection. 
leading the product multi-discipline design in all fields including work with thermo-mechanical, signal/power integrity, software, and optics teams and more. 
hands on lab work to bring to design to life, evaluate and improve the product performances. 
work with multiple operational groups inside and outside the company such as qualification, suppliers, and manufacturers to scale the product from lab to mass production high runner. 
learning to use new technologies to enable improvement for generation to generation.

Were looking for an experienced SW Team Manager to join our Simulators Team, where you'll lead the design and development of our hardware simulators - functional and performance models that serve as the source of truth, drive architectural exploration and compiler optimization.
Our simulators model diverse cores within a cutting-edge SoC designed to accelerate Big Data and Database Analytics.
You will collaborate closely with hardware and software teams, contributing to co-design efforts that influence architecture, tooling, and system-level behaviour.
Responsibilities:
Lead & grow a team of experienced engineers
Develop new hardware simulators and continue evolving existing one.
Collaborate with Architecture, VLSI, and Software teams to drive co-design initiatives.
Provide insights that influence chip architecture, compiler optimization, and system-level performance.
Develop tools that drive the chip development cycle.

we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities

Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects

in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and verification closure. you will verify digital designs, collaborate with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner cases and expose all types of bugs. you will manage the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with strategic value add (sva) and industry-leading formal tools.
identify and write all types of coverage measures for stimulus and corner cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

widely considered to be one of the technology worlds most desirable employers, our company is an industry leader with groundbreaking developments in high-performance computing, artificial intelligence and visualization. the gpu, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. our work opens-up new universes to explore, enables amazing creativity and discovery and powers what were once science fiction inventions from artificial intelligence to autonomous cars.
 
the senior power design engineer will be responsible to design our datacenter products such as switches, adaptors and electro-optical cables. in this role you will be responsible for all aspects of product from definition, design to execution. continuously renewing your academic foundation, validated by active exposure of industry experience. interact closely with company experts and become an integral member of a global collaborative team. join us and be a part of this fast paced, dynamic environment!
 
what you will be doing:
design datacenter system power solutions, such as switches, adapters and electro-optical cables.
perform validation of system power solutions.
design power solution TEST platforms.
collaborate, provide feasibility analysis, present options and review of odm power solutions.
execute system power bring-up and debugs.
define system power testing specifications.
engage with vendors to resolve system power issues.

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.

Key Responsibilities

Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs
Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners
Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy
Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids
Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs
Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA
Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)

we are now looking for a senior hpc site reliability engineer to join our mission and continue improving our hpc infrastructure. a meaningful part of nvidias strength is our unique and advanced development tools and environments that enable our incredible pace of innovation. we are looking for architects to help us evolve the way our private compute cloud is architected and optimized. 
what you will be doing: 
provide leadership in the design and implementation of our large-scale compute cloud that enables the world's top chip modelers, designers, and deep learning experts to invent groundbreaking technology.
identify architectural changes or completely innovative approaches in our cloud architecture and design. 
help with strategic challenges we encounter, including: effective resource utilization in a heterogeneous compute environment, evolving our private/public cloud strategy, capacity modeling, and planning for multi-year growth and scaling across our global computing environment!

lead performance research and evaluation of advanced networking technologies supporting ai workloads, including llm training and inference at supercomputing scale.
define end-to-end performance TEST plans and methodology for next-generation networking hw and networking technologies, including performance expectations and target kpis.
drive benchmarking, profiling, reporting, and deep performance characterization of networking workloads and offload features.
collaborate closely with simulation, architecture, chip-design, firmware, and software teams to assess performance tradeoffs and identify bottlenecks.
perform deep root cause analysis (rca) for performance gaps and stability issues, and drive cross-team mitigation plans.
develop and enhance performance analysis tools, automation frameworks, and scalable methodologies for cluster-level performance evaluation.
own performance observability efforts, including telemetry pipelines, dashboards, and job-level performance analytics.

We are a pioneering force in the autonomous vehicles (av) industry. join us to build the brain behind the car - a large-scale, multi-task neural network that powers the core of our autonomous stack. youll design and train cutting-edge deep learning models tailored for our custom eyeq chip, tackling end-to-end challenges and deploying real-world solutions. from novel architectures and advanced training techniques to performance tuning under tight constraints, youll work closely with software and hardware teams to turn research into high-impact, production-ready systems. if youre a brilliant, hands-on researcher with a passion for shaping the future - this is your launchpad.
why us?
our team is at the forefront of our most advanced ai efforts.
as a central hub for deep learning innovation, were trusted with designing the core neural network architecture that powers the companys flagship products.
if youre seeking a high-impact role among top-tier researchers and developers - this is the place to be.

we are seeking a highly motivated and skilled radar system architect to join our team, focusing on automotive imaging radar systems. this role is pivotal in bridging the gap between our cutting-edge radar technology and our automotive customers' evolving needs. as the key technical focal point, you will lead customer engagements, manage system -level requirements, define system architecture in multiple domains and ensure successful integration and performance of our radar solutions in real-world automotive applications. what will your job look like?
define high level requirements for cutting-edge, automotive imaging radar
design system architectures and flows for critical functions, such as power management, safety monitoring and security
research and architecture for improving radar kpi's and capabilities
engage with customers, analyze and understand customer requirements
work closely with sw, algo, hw, vlsi and validation teams

We are looking to hire a talented Verification Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips. If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities
Collaborate with architecture and design teams to define and implement comprehensive testcases for NN processor and SoC blocks and flows.
Maintain, enhance, and scale the UVM‑based verification environment to support efficient and robust verification.
Own end‑to‑end verification of system flows to ensure the design is fully functional, correct, and meets performance expectations.
Drive root‑cause analysis and debug across RTL, testbench, and system layers to ensure high‑quality design closure.
Define, track, and close functional and performance coverage to guarantee verification completeness.
Continuously improve verification methodologies, automation, and workflows to increase productivity and coverage efficiency.

we are now looking for a senior ai system security architect! we are looking for an outstanding technical security architect with system architecture focus to design, validate, and guide implementation of secure architecture of its core products. the candidate is expected to: define problems and deliver highly innovative solutions that lead to significant differentiation in the industry, translate customer needs into architectural, technical & strategic direction, and help to resolve objectives & long-range goals of the security organization. leaders in this role will help reduce risk, threats, and vulnerabilities indata center products and services.
what youll be doing:
own the security requirements for networking systems in a variety of product lines.
work with technical and senior leadership staff to turn business directives into functional implementations.
collaborate between multiple business units and development groups to ensure a robust and secure product posture, from design to implementation in multiple system level products
provide hands-on security engineering expertise across a wide variety of platforms and services
provide strategic and tactical expertise in orchestrating, securing, deploying solutions; and in defining relative architectures.
this role extends across multiple groups and excellent working knowledge in the following areas of expertise is necessary for success:
designing system security architecture at hyperscale
Embedded systems security architecture and design
deep, low level understanding in root of trust (rot) technologies
networking security protocols and concepts
operating systems security and sw security concepts

We are now looking for a Senior HPC Site Reliability Engineer to join our mission and continue improving our HPC infrastructure. A meaningful part of NVIDIAs strength is our unique and advanced development tools and environments that enable our incredible pace of innovation. We are looking for architects to help us evolve the way our private compute cloud is architected and optimized.

What you will be doing:
Provide leadership in the design and implementation of our large-scale compute cloud that enables the world's top chip modelers, designers, and deep learning experts to invent groundbreaking technology.
Identify architectural changes or completely innovative approaches in our cloud architecture and design.
Help with strategic challenges we encounter, including: effective resource utilization in a heterogeneous compute environment, evolving our private/public cloud strategy, capacity modeling, and planning for multi-year growth and scaling across our global computing environment!