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we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You wont just be using tools; youll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.


Key Responsibilities

Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes
Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows
Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics
Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.


Key Responsibilities


Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
Own the design database structure and version control to ensure team alignment and data integrity
Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.

Key Responsibilities

Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs
Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners
Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy
Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids
Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs
Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA
Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)

we're seeking a highly skilled Physical Design Engineer specializing in EMIR & Power Integrity to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will execute the Electro-Migration and IR Drop (EMIR) analysis and sign-off from block level to full-chip, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. You will be responsible for validating power grid architectures to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Execute static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from the block level through to full-chip sign-off
Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Work with Physical Design teams to implement optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Collaborate closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Perform root-cause analysis for voltage drop violations and EM risks, proposing and implementing layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with strict foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

As a Staff Physical STA Expert , you will hold the keys to silicon success. You will be leading the STA activities end-to-end from Chip partition, Time budgeting through signoff of all the chips we develop. You will build and lead the STA team to run several chips signoffs in parallel. In addition, You will define the sign-off methodology for chips that power the worlds most advanced AI clusters. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

Take full ownership of the STA flow and sign-off methodologies. You will establish the rigorous criteria that ensure our products succeed in the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams. You will lead timing reviews and work closely with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints from the ground up, ensuring they are robust across multi-scenario environments
Tackle the challenges of cross-chip clock distribution networks and sophisticated margining techniques, ensuring robust silicon across all process corners
Have a passion for better workflows? Youll participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and in-house automation to make our sign-off process faster and smarter

seeking a skilled and motivated Data Scientist. This individual will play a pivotal role in identifying key data points for collection, developing strategies to accumulate data and deriving actionable insights an anomaly based on a solid foundation of relevant know-how. Also, will also be responsible for creating, testing, and deploying scripts and methods for data collection and analysis to support decision-making. The Engineer will collaborate with cross-functional teams to identify critical data sources to determine the most effective data collection strategies, will develop automated and scalable data collection pipelines, will ensure data quality, integrity, and consistency across all sources and may use AI techniques to refine the results toward failures predictions.

We are looking for a talented leader to join the R&D department and manage development teams.As Group Manager you will own the end-to-end delivery of software releases, ensuring engineering processes are effective and compliant while maintaining a high bar for quality. Strategic oversight and accountability keep the organization aligned and moving forward.
As Group Manager you will actively participates in product vision, roadmap, and strategy forums, contributing an engineering perspective and ensuring development capabilities are reflected in business decisions. Cross-departmental initiatives are driven in close partnership with product, QA, and operations. On the technical side, the Group Manager participates in strategic discussions on technologies, architecture, and development methodologies, and drives the integration of AI tools into the development ecosystem.
Partner with team leads to plan and execute projects, ensuring teams have the necessary specifications, direction, and resources to deliver effectively, with realistic timelines and clear accountability for meeting them.
Monitor and report the status of projects across all teams, ensuring work is assigned appropriately and that project scope is clearly defined before execution begins.
Develop a deep understanding of the domain, existing systems, and architecture, continuously looking for opportunities to improve usability, maintainability, and overall system quality.
Serve as the technical representative in discussions with customers and cross-functional R&D teams, both within and outside the organization.
Mentor and support team members in resolving technical and interpersonal challenges, while overseeing HR responsibilities including performance management, vacation approvals, and corrective actions where needed.
Provide leadership and guidance that motivates team members, drives performance, and supports their long-term career development.

We are looking for a full-stack software engineer to join our team!
Youll be joining a squad focused on building features for our large-scale multi-tenant system, enabling our customers to better manage their business, infrastructure, and security.
Responsibilities:
As a Full-Stack Developer, you must be comfortable with front-end (Angular) and back-end (C# .Net Core) development. You will build end-to-end solutions encompassing web/back-end development, monitoring, scaling and optimizing to make the products simple at a massive scale.
You will be empowered to drive innovation by coming up with new and exciting ideas to creatively solve issues and proactively look for opportunities to improve the design, interface, and architecture of our cloud platform.

We are looking for a dynamic and experienced full-stack team lead!
As the Team Leader, you will play a pivotal role in overseeing and coordinating the critical domain responsibilities essential to our organization's smooth operation. Your team will manage and optimize key processes and activities that directly impact our platform's success.
Responsibilities:
As a Full Stack Team Lead, your responsibilities will include managing and mentoring a team of full stack developers, leading a software development squad, planning and executing new and existing projects, reviewing designs, and finding ways to empower engineering teams to build better products.
As we work directly on our cutting-edge products, hands-on coding as part of the team is a crucial part of the role.

Were looking for a strategic and hands-on Enablement Team Lead to own onboarding and ongoing enablement across our expanding global Revenue organization.
This role will support Sales, CS, Presales, CX and Partners/Resellers and Support, while embedding AI into enablement strategy, execution, and adoption.
What Youll Do:
Global Revenue Enablement:
Lead onboarding and continuous enablement across multiple offices, cultures and time zones.
Own onboarding for all new hires, including product knowledge and role-based training
Adapt enablement programs to different teams, roles and motions.
Incorporate industry training to ensure deep understanding of customers and their pains.
Create and execute an ongoing product training and skills improvement plan.
Build and execute a structured Enterprise enablement plan including: Discovery frameworks, demo methodology, competitive positioning, industry trends and effective use of marketing materials.
Collaborate with Product Marketing on competitive analysis and internal collateral.
Partner with Product to deeply understand new features and train the Revenue org on value and capabilities.
AI-Driven Enablement Leadership:
Act as the AI lead within the Revenue Enablement domain.
Embed AI tools and automation into onboarding and ongoing enablement workflows.
Leverage AI to improve training personalization, content creation, knowledge management and productivity.
Identify practical AI use cases that enhance enablement effectiveness and scalability.
Continuously explore new AI capabilities relevant to Revenue Enablement and implement them where impactful.
Infrastructure, Processes & Measurement:
Collaborate with RevOps on enablement for new BizApps processes.
Manage and optimize internal LMS (Workramp) and Partners Academy.
Design feedback infrastructure for managers and teams (live & asynchronous).
Define, track and report enablement KPIs and business impact.
Use tools such as Workramp, Rise360, Monday and Gong.
This role is ideal for someone who combines strategic thinking with execution excellence, thrives in complexity, and wants to lead AI-powered transformation across a global Revenue organization.

Development of complex information systems in eMerge.
Learning and expertise in SQL and with unique internal technology.

We are seeking a highly skilled and experienced Senior Software Engineer with at least five years of hands-on experience in software development. In this role you will design and develop a multi-layer SW stack for a quantum computers operating system, working closely with product, quantum physicists, System engineers, and HW developers. You will have to be familiar with all system components, take part in the integration, debugging and testing of a highly complex system.
Responsibilities
our company OS Software Architecture: Shape the architecture, Lead designsfor new modules that will create the quantum computers operating system.
our company OS Software Development: Implement new features in the system.
Partner across disciplines: Work closely with product, hardware engineers, physicists and system engineers to integrate software with quantum hardware components. Help triage production issues and translate lab/field feedback into product improvements.
Product Quality: Raise the bar on quality. Add robust automation, unit/component tests and resiliency checks. Drive safe rollouts, versioning and backward compatibility
Performance Optimization: Optimize software for performance and latency.

looking for a Medical Data Analyst to join our growing Implementation group, reporting to our Squad Lead. The ideal candidate will be responsible for ensuring the successful implementation of new clients and analyzing both historical and real-time client data.



As a Medical Data Analyst, you will:

Analyze and understand clients business objectives, coding patterns and methodologies in order to configure Clinical language understanding engine for optimal performance.
Support clients throughout the technical integration and engine onboarding processes, documenting solutions and proactively improving client-specific outcomes through hands-on work with our codebase to adjust configurations, scripts, and rules.
Actively troubleshoot, investigate, and resolve coding discrepancies, distinguishing issues arising from client-specific configurations versus core engine functionality.
Provide solutions for alerts and incoming escalated tickets from our customers.
Collaborate across multidisciplinary teams - including engineers, linguists, medical doctors, product managers, customer success managers and coders -to ensure smooth project execution and effective communication.

seeking an experienced and visionary Head of Research to lead, shape, and advance the future of AI innovation across the organization. In this role, you will own the research strategy end-to-end - from long-term roadmap design to hands-on exploration, and guide a multidisciplinary team of NLP research engineers and linguists toward breakthroughs that elevate our core medical coding engine.

You will play a key role in the company, balancing exploratory research with high-impact product delivery. You will partner with Product, Engineering, and executive stakeholders to identify strategic opportunities, drive prioritization, and translate research capabilities into real-world outcomes at scale.

Responsibilities:

Manage and mentor a multidisciplinary research team while driving both technical excellence and personal growth.
Define the long-term research roadmap aligned with product and business objectives.
Lead the full research lifecycle, from ideation and feasibility studies to experimentation, evaluation methods, and production-ready delivery.
Evaluate and introduce new research capabilities and emerging trends such as LLM-based reasoning, semantic/graph modeling, hybrid rule-learning, and other frontier techniques.
Continuously track scientific trends to maintain a state-of-the-art research practice.
Collaborate closely with Product and Engineering teams to translate domain challenges into algorithmic solutions with measurable product impact.
Represent the Research function at leadership forums, communicate priorities and outcomes, and align stakeholders around research strategies and milestones.