לוח משרות דרושים הייטק תוכנה

We are looking for a skilled QA Automation Engineer (backend oriented) to join our Parking domain. You will play an important role in ensuring the quality of mission-critical systems that serve millions of users daily.
The majority of the role is automated testing combing AI Skills but combines manual as well.
This is a great opportunity for somebody who want to enhance infrastructures, develop in engineering and great best practices and handle scaled distributed systems based on AWS.
Responsibilities
Design and develop automated tests end to end for new and existing features, execute mainly Backend orientation API tests, including automation for backend services.
Apply AI tools (e.g., Cursor, Claude Code) in day-to-day work to generate code, build automation, and continuously improve testing workflows.
Write and maintain detailed test cases and documentation.
Identify, record, and track software defects and issues, ensuring timely resolution.
Work with tools such as Qase.
Collaborate with cross-functional teams to understand product requirements and design effective testing strategies.

In this role, you will take full ownership of complex backend projects end-to-end in a high-scale, consumer-facing domain. We value engineers who think ahead, identify problems before they surface, and drive solutions independently -- while collaborating effectively across teams.
Responsibilities
Own complex backend projects end-to-end: from functional spec through architecture, development, deployment, and production monitoring.
Design, develop, and maintain scalable backend microservices serving millions of daily users.
Build and manage cloud-native, event-driven architectures on AWS and distributed systems.
Design and build reusable AI-driven components (e.g., sub-agents, skills, and templates) to streamline workflows and improve system efficiency, leveraging modern AI tools and technologies
Proactively identify technical debt, performance bottlenecks, and architectural gaps -- and drive initiatives to address them.
Collaborate with cross-functional teams including Product, DevOps, Mobile, and QA.

Were seeking an exceptional Senior Backend Engineer to join our Platform team. This team is at the heart of what we do- building the tools and infrastructure that enable to scale rapidly while maintaining the quality and reliability our users depend on.

Responsibilities

End-to-End Ownership: Lead projects from design through production, taking responsibility for technical decisions and their outcomes
Platform Architecture: Design and evolve scalable backend systems that power our core products
Infrastructure & Reliability: Build robust, high-performance APIs and services that handle production workloads at scale
Developer Experience: Create internal tools and frameworks that accelerate development across the organization
Technical Leadership: Drive architectural discussions, mentor team members, and raise the bar for engineering quality

We are seeking a Solutions Engineer to become an integral part of its team, dedicated to offering technical guidance and assistance. The ideal candidate will have the chance to cultivate connections with pivotal clients and play a crucial role in advancing the sales of our products. If you aspire to collaborate closely with our sales, product and R&D team, delivering technical expertise, demonstrations, and solutions to our customers, we would love to hear from you!

What will you do?

Providing technical guidance and support to prospects and customers
Explaining products and services to customers and work closely with them to understand their technical requirements and translate them into effective solutions.
Assisting with product demonstrations, presentations and webinars.
Provide training to clients, both in person and remotely, to ensure they can effectively use our products.
Respond to technical inquiries and provide in-depth information to clients.
Support the closing of deals by addressing technical concerns and objections.
Gather feedback from clients and the sales team to help improve our products and services.

Tavily team is building the search engine for AI agents. We believe the future of work will be led by AI agents, and that requires restructuring how the web is accessed. Our Search API provides web access for AI agents, enabling real-time internet search optimized for LLMs and Retrieval-Augmented Generation (RAG). We are backed by leading investors and serve developers and enterprises worldwide. Our team is fast-moving and ambitious. We ship quickly, iterate constantly, and care deeply about impact.
As a Software Engineer - Scraping Specialist, youll build the systems that power how AI interacts with the live web. Youll design and implement large-scale, intelligent web acquisition pipelines, making sense of an ever-changing online ecosystem and transforming it into structured, high-quality data.
This role blends technical understanding of browsers, networks, and automation with hands-on engineering. Youll work on adaptive systems that navigate modern websites, understand evolving web interaction ,detection systems, and gather meaningful information safely, efficiently, and at scale.
Your work will directly shape Tavilys ability to provide AI agents with accurate, real-time knowledge of the world , bridging the gap between the open web and intelligent reasoning.
What Youll Do
Build distributed data acquisition systems that capture and structure the live web
Investigate and analyze browser internals, fingerprinting, and anti-automation systems to develop stealthy, adaptive orchestration layers
Prototype and deploy intelligent automation frameworks using Playwright, Puppeteer, and low-level browser control protocols (CDP)
Conduct hands-on research into network flows, JavaScript-based protections, and emerging web standards affecting automation
Collaborate with AI and infrastructure teams to integrate real-time web data into retrieval pipelines and LLM-powered agents
Translate deep technical insights into production-grade components, balancing research freedom with engineering rigor
Continuously evolve Tavilys capabilities in resilience, speed, and authenticity of web interaction.

we are looking for a Senior Data & Business Analyst to lead analytics and business health indicators across our operational and company-wide domains. This is a senior individual contributor role combining strategic thinking, deep hands-on analytical execution, and strong cross-functional business partnership. Youre welcome to work in our office in Tel Aviv.
The role requires the ability to operate at two levels simultaneously: understanding the full business picture while diving deep into complex datasets and technical execution. You will work closely with Operations, Finance, and other cross-functional teams to improve efficiency, transparency, and decision-making across the organization.
Your responsibilities will include:
Own end-to-end analytics for core operational processes.
Define, build, and maintain company-level operational and business health KPIs.
Translate ambiguous, cross-functional business questions into structured analytical frameworks.
Write advanced, high-performance SQL to extract, model, and analyze complex datasets.
Lead deep-dive analyses to uncover operational inefficiencies, financial impact, and process gaps.
Connect data across systems and explain upstream and downstream business impact.
Independently identify high-impact problems worth solving, not only respond to requests.
Drive cross-functional analytical initiatives at a company-wide level.
Present insights, trade-offs, and recommendations to senior leadership.
Synthesize complex findings into concise executive-level narratives.
Influence decisions and drive measurable impact based on data.
Act as a central analytical partner across multiple business domains.
Lead initiatives and move stakeholders forward without direct authority.

We are looking for a highly skilled SW developer Expert with substantial Object-Oriented experience in a multi-disciplinary environment to join our R&D group in Israel (Rehovot).
You will be a part of a talented software team that is currently developing the next generation of 3D printers, using cutting-edge technology and constantly looking for new ideas and improvements.
What you will be doing:
Lead development tasks through all stages - gathering requirements, designing, implementing (mostly using C++ and C#) and following integration on the 3D printers themselves.
Work closely with System and HW engineers, SW developers, QA and many more.
Perform design and code reviews
Constant collaboration and knowledge sharing with the SW team.

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As an Expert EMIR & Power Integrity Lead, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will own from block level to full-chip the Electro-Migration and IR Drop (EMIR) methodology, analysis, and sign-off, working at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

You will be responsible for defining power grid architectures and validating that products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes. Your work will directly impact the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the worlds largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

SoC Top level Ownership and oversee the Chip convergence.
Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects

As a Physical Design CAD Lead, you will be responsible for the physical implementation environment. Your primary mission is to build, optimize, and support the automated flows from RTL to manufacturable GDSII tape-out. You will own the flows, Database and will support the whole PD team to optimize their blocks for Power, Performance, Timing while keep the team aligned on Methodical, Efficient and balanced work Environment.


Key Responsibilities

Design and maintain automated flows for Synthesis, Place & Route, and Floor-planning
Develop robust environments for Static Timing Analysis, Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write custom plug-ins and scripts to extend the capabilities of vendor tools, tailoring them to our specific process node constraints and flows
Create automated "dashboards" and feedback loops to help design teams track and improve Power, Performance, and Area metrics across iterations
Collaborate with EDA vendors (Synopsys, Cadence, Siemens/Mentor) as consulters for our developed flows and results analysis     

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we're seeking a visionary Physical Design Subsystem (Multiple IPs/Partitions) Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As the Physical Design Subsystem (Multiple IPs/Partitions) Lead you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SubSystem with your team for chips that drive the worlds largest AI clusters. You will lead the team and the transition from RTL to GDS, ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

Build and mentor a high-performing Partitions team , owning the end-to-end execution from Synthesis to Signoff
Take full ownership of Subsystem physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Lead and guide external contractors and global partners to ensure seamless execution and delivery
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon

As a Principal/ Senior Principal ASIC Architect, you will be the blueprint creator for the future of AI infrastructure. You won't just follow specifications-you will lead the definition and execution of next-generation ASIC solutions targeting hyperscale data centers. From analyzing market requirements to guiding products through their entire lifecycle, your influence will be etched into the silicon that enables the next era of scale-up and scale-out connectivity. If you thrive on solving complex, unnamed challenges and want to shape the architectural foundation of AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Architectural Definition & Strategy

Lead the architectural definition of next-generation ASICs, translating complex market requirements into elegant, high-performance hardware specifications
Drive technical decision-making that balances power, performance, area, and cost (PPAC) to maintain competitive edge in the hyperscale ecosystem
Leverage deep domain expertise to integrate industry standards (Ethernet, UALink, PCIe) into cohesive systems solving demanding AI infrastructure challenges
Product Lifecycle Ownership

Own the architectural journey from initial concept through design, implementation, tapeout, and mass production
Ensure final products deliver on performance promises and meet hyperscaler requirements
Drive architectural exploration and performance modeling to validate design decisions
Technical Leadership & Cross-Functional Collaboration

Act as the technical North Star for the engineering organization in Israel
Collaborate across Architecture, Design, Verification, DFT, and Backend teams to ensure seamless execution
Influence and align cross-functional teams around unified technical vision through strong communication and leadership

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation

Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization

Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration

Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration