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our company is leading groundbreaking developments in artificial intelligence, high performance computing and visualization. the gpu -- our invention -- serves as the visual cortex of modern computers and is at the heart of our products and services. our work opens up new universes to explore, enables groundbreaking creativity and discovery, and powers inventions that were once considered science fiction, including artificial intelligence to autonomous cars. come work for the team that brought to you nccl, nvshmem & gpudirect. our gpu communication libraries are crucial for scaling deep learning and hpc applications! we're seeking a Senior Software Architect to help co-design next-gen data center platforms and scalable communications software.
DL and hpc applications have a huge compute demands and already run at scales of up to tens of thousands of gpus. gpus are connected with high-speed interconnects (e.g. nvlink, pcie) within a node and with high-speed networking (e.g. infiniband, ethernet) across nodes. efficient and fast communication between gpus directly impacts end-to-end application performance. this impact continues to grow with the increasing scale of next generation systems. this is an outstanding opportunity to advance the state-of-the-art, break performance barriers, and deliver platforms the world has never seen before. are you ready to build the new and innovative technologies that will help realize our vision?
what you will be doing:
investigate opportunities to improve communication performance by identifying bottlenecks in today's systems.
design and implement new communication technologies to accelerate ai and hpc workloads.
explore innovative solutions in hw and sw for our next generation platforms as part of co-design efforts involving gpu, networking, and sw architects.
build proofs-of-concept, conduct experiments, and perform quantitive modeling to evaluate and drive new innovations.
use simulation to explore performance of large gpu clusters (think scales of 100s of 1000s of gpus)

conduct in-depth performance characterization and analysis on large multi-gpu and multi-node clusters.
study the interaction of our libraries with all hw (gpu, cpu, networking) and sw components in the stack
evaluate proof-of-concepts, conduct trade-off analysis when multiple solutions are available
triage and root-cause performance issues reported by our customers
collect a lot of performance data ; build tools and infrastructure to visualize and analyze the information
collaborate with a very dynamic team across multiple time zones

our company is leading the way in groundbreaking developments in artificial intelligence, high performance computing and visualization. the gpu, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars.
come work for the team that brought to you nccl, nvshmem & gpudirect. our gpu communication libraries are crucial for scaling deep learning and hpc applications! we are looking for a motivated partner enablement engineer to guide our key partners and customers with nccl. most DL /hpc applications run on large clusters with high-speed networking (infiniband, roce, ethernet). this is an outstanding opportunity to get an end to end understanding of the ai networking stack. are you ready for to contribute to the development of innovative technologies and help realize our vision?
what you will be doing:
engage with our partners and customers to root cause functional and performance issues reported with nccl
conduct performance characterization and analysis of nccl and DL applications on groundbreaking gpu clusters
develop tools and automation to isolate issues on new systems and platforms, including cloud platforms (azure, aws, gcp, etc.)
guide our customers and support teams on hpc knowledge and standard methodologies for running applications on multi-node clusters
document and conduct trainings/webinars for nccl
engage with internal teams in different time zones on networking, gpus, Storage, infrastructure and support.

we are now looking for a power optimization and analysis engineer! our company prides ourselves on having energy-efficient products. we believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. as part of the u/arch team in the switch group, you will be responsible for analyzing full chip and unit-level power data and driving the fe/be asic teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our products become more energy efficient. key responsibilities include developing techniques to model, analyze, and reduce power consumption of our switches product line.
as a member of switch u/arch team, you will collaborate with architects, performance engineers, software engineers, asic design engineers, and physical design teams to study and implement power analysis and reduction techniques for our next generation switches. your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.
what you'll be doing:
use internally developed tools and industry standard pre-silicon gate-level and rtl power analysis tools, to help improve product power efficiency.
develop and share best practices for performing pre-silicon power analysis.
perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
interact with architects and rtl designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
select and run a wide variety of workloads for power analysis.
prototype new architectural features in verilog and power analysis.

we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies. our switch team delivers world class bridge and router solutions for hpc, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of core technology.
you will work on developing new formal verification methodologies and tactics.

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you will be doing:
join tel aviv group, working in a combined design and verification team which develops phy layer ip within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, fw and post-silicon validation.

we are now looking for a senior chip design engineer to join our switch silicon team. as a chip design engineer networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! 
what you'll be doing:
work in a design/verification team which develops core units within the switch silicon.
micro-architecture of rtl verification environments planning for units and modules.
design rtl of units/blocks according to arch. specifications under challenging constraints with high orientation to power, area, and performance.
rtl synthesis, timing, supporting verification, and silicon post to activities.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw.

we are now looking for a best-in-class Verification engineer to join our outstanding gpu-networking silicon engineering team. as a dv engineer at gpu-networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry - gpu super-chip. 
what youll be doing:
work in a dv (design verification) team that has a global responsibility over deliverable units and clusters to the silicon gpu
integrations and full-chip models
verification of chip blocks/entities according to specifications under challenging constraints
ramp-up and run dv tasks on emulation platform

we are seeking a highly motivated high-performance system architect to join our team of experts and help shape the future of high-performance and ml / ai computing. our next-generation nvl systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced ai models such as gpt and deepseek. as a high-performance system architect at nvidia, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.
what youll be doing:
define the nvl system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
research various of solutions to enable the next large-scale-high-performance computing clusters. the position spans over various layers from algorithms, software, firmware, and hw.
collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people.
today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an our employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team that is building ai platform for operating ai factories to make a lasting impact on resilient operations of ai clusters.
what will you be doing:
you will bring together and understand internal and external customer requirements to improve ai cluster resiliency and design aiops-based solutions that address these needs.
develop automated workflows for issue detection and root cause analysis and closely collaborate with operators to debug sophisticated, Full-Stack ai cluster problems. we will bring to bear the findings for product improvements!
deliver compelling technical presentations and lead hands-on demos or training. you'll also handle evaluation deployments (poc/pov) and ensure smooth, reliable installations by staying engaged and encouraging throughout the customer journey.

as a Senior Software Architect in the gpu networking architecture team, you will define software defined networking architectural solutions. you'll also be part of a team of specialists who span across numerous technological fields related to the modern data center, such as distributed ai and deep learning systems, networking operating systems, virtualization, Storage, and more.
what youll be doing:
define system and software architecture for software defined networking (sdn) of ground breaking emerging ai networks which involves innovative software and hardware.
be an active member in setting the use-cases and metrics for monitoring complex high-speed networks control-plane.
work closely with various groups within nvidia to bring ai network technologies to reality, including gpu and switch hw and sw teams, product as well as fellow architects.

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. we seek an senior sw performance engineer to join our performance verification team. as a performance engineer at our company, you will have to work closely with our development and architecture teams responsible for ethernet ai solution and gain a deep understanding of our products and technologies.
what youll be doing:
participate in an international team of software engineers working on products for testing our products
build automated verification environment for high-end hardware and software which is at the forefront of innovation
identify, analyze, and report software defects, inconsistencies, and other quality issues.
drive improvements for performance, quality, stability around sw acceleration solutions.
stay up to date with industry standard methodologies, new technologies, and emerging trends in software verification.

we are seeking a senior deep learning Research Engineer for an excellent opportunity. this role provides an outstanding opportunity to engage in groundbreaking innovation and contribute to the advancement of generative ai technologies. you will work with pioneering methodologies and tools, crafting solutions that push the boundaries of ai capabilities.
 
joining our company means being part of a phenomenal team renowned for its inventions, such as large language models (llm's), and contributing to impactful work that influences various applications. we offer a collaborative environment that fosters professional growth. you will have the opportunity to collaborate with some of the brightest minds in the field, both within our global network and with leading companies worldwide, making this role perfect for those passionate about advancing ai technology and eager to make a significant impact on the future of the field.
 
what you'll be doing:
invent and build ground breaking techniques for efficient llm's and multi-modality models.
contribute to our ai enterprise software to ensure robust and scalable solutions.
collaborate with internal and external teams worldwide to drive research and development in llm's and multi-modal learning, using different professions and resources across the company.
partner with leading scientific organizations and industry pioneers to remain at the forefront of technological advancements and integrate the latest innovations into practical applications.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.