* Manage and build a world class team managing ASIC design, micro-arch, SDC constraints and integration efforts of the project.
* Translate high level goals to measurable plans and milestones. Lead RTL design, quality checks, and manage schedule for on-time delivery of key IPs.
* Work with verification and physical design teams to achieve high quality design.
* Interface with IP teams and manage schedule and delivery of IPs for successful TO.
* Guide and mentor junior engineers as required.
* Hire and retain tier one engineers and foster teamwork with cross functional collaboration.
* Build a culture of execution excellence coupled with innovation.
* Build a team of hard-working and passionate leaders as we scale.
* Maintain close interactions with NPI, Packaging, DFT, Architecture teams.
* Own power, performance and area optimization of design.
Requirements: * 12+ years minimum of hands-on experience in ASIC design.
* BSc in Electrical Engineering or Computer Science or equivalent industry experience.
* Demonstrable experience as a leader for large ASIC developments in advanced process nodes.
* Drive ASIC design methodology and flow from concept to release.
* Expert understanding of both FE and BE ASIC flows.
This position is open to all candidates.