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our team in israel is looking for a senior hardware Validation engineer to join the board design hardware team. the team leads the development of networking infrastructure for our next-generation data centers, focusing on accelerated performance and optimized end-to-end gpu connectivity. we are looking for a hands-on and detail-oriented practical engineer with strong lab skills, who enjoys working in a dynamic, multidisciplinary environment.
what you'll be doing:
perform board bring-up, validation, and debugging activities in the lab
operate lab equipment such as oscilloscopes, power supplies, logic/spectrum analyzers, and multimeters
support hardware investigations by reading schematics, analyzing layouts, and completing TEST procedures
document TEST results and communicate findings clearly to engineering teams
work closely with electrical, mechanical, thermal, and system engineers throughout the development cycle.

our networking team is looking for an outstanding candidate who thrives in a multifaceted environment, to manage exciting sw releases for our leading fw, sdk and nos switch products. taking care of world-class technologies in the areas of data centers, cloud, software defined networks, security for the most sophisticated markets and customers. the switch products supports ethernet and infiniband protocols, delivering a broad range of sophisticated networking, Storage, and security services for the cloud, sophisticated compute and ai workloads. the candidate will need to ensure the release is delivered on time and in high quality, coordinate between development and testing groups and between global sw groups. in addition the role will require to gain good understanding of products dependencies.
what you'll be doing:
be an effective leader in crafting and driving a delivery high quality sw in an efficient way.
partner with engineering, operations, architecture and marketing to coordinate the release of the products and ensure release will meet the schedule and with high quality
take full ownership on the fw, sdk, nos products from the kickoff to signoff.
work with planning and tracking systems to lead the release progress, and build release indicators.
partner with the QA teams to ensure alignment of all tests between the development, verification and QA groups.
conduct release meeting and communicate release status. resolve issues when they appear and raise red-flags when needed.
collaborate with teams across the globe to drive process changes that can help improve development and release workflow.
define and improve process, guidelines, checklists across switch sw group.

we have been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. it's a unique legacy of innovation that's fueled by great technology-and amazing people. today, we're tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing what's never been done before takes vision, innovation, and the world's best talent. as a member of our team, you'll be immersed in an inclusive, supportive environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the world.
we are a fast-growing world leader supporting the most powerful supercomputers worldwide. our networking products lead the industry and connect thousands of gpus. we make outstanding artificial intelligence possible through innovative networking and computing integration. we value our people and seek excellent individuals to join us! we are looking for an experienced packaging, technology and manufacturability expert to help us build the next generation of networking products. our networking devices depend heavily on advanced packaging methods like chiplet integration, 2.5d interposers, and co-packaged optics. packaging choices influence schedule, cost, and yield equally with the silicon. we are looking for a packaging and manufacturability lead who will own the package technical view across our chip programs. this role partners with the advanced technology group to push technology limits in future products. joining an outstanding team, you will highlight package risks early, bring manufacturability into design choices before they are fixed, and find co-design approaches that improve module yield. join us in making an impact on all networking products and pushing the boundaries of technology.
what you'll be doing:
lead the technical assessment of package risk across our chip programs - identifying failure modes in substrate, interposer and assembly integration before they reach silicon, quantifying their cost and schedule impact, and bringing them to program and technology reviews with a clear position
drive new approaches to manufacturability across the board (package, substrate, interposer, silicon), spanning yield improvement, capacity and supply review, TEST strategy, thermal and assembly process maturity. push co-design levers such as tolerance relaxation by design, testability before attach, design margins, and redundancy and partial-module recovery
analyze module yield mechanics, reconcile predicted versus actual yield on units returning from assembly, and convert the findings into concrete design guidance
evaluate emerging packaging and photonics technologies, including outside partner solutions, and define our product requirements - working closely with our advanced technology group.

our performance group is seeking a technical nic & dpu performance research & analysis engineer to drive end-to-end performance strategy, characterization, optimization and hw offload accelerations for next-generation network interfaces and data processing units (dpus).
in this role, you will analyze and accelerate critical networking and Storage technologies and protocols powering multi nodes ai clusters. you will profile performance across the complete hardware-to-software execution stack-stretching from dpu arm cpu subsystems and pcie to high-speed rdma, spdk, and doca acceleration pipelines.
what you'll be doing:
data -path optimization: drive end-to-end benchmark plans, performance characterization, expectations and optimizations for nics and dpus deployed in distributed ai and cloud data centers.
Full-Stack profiling: profile low-level memory, pcie, host cpu, and dpu asic execution paths to identify micro-architectural stragglers, queue bottlenecks, and tail-latency outliers.
Storage & network acceleration: hands-on acceleration and offloading of Storage (spdk, nvme-of, virtio) and networking protocols (rdma/rocev2, tcp/ip, doca).
ai-assisted workflow automation: leverage ai agents, autonomous scripts, and automated regression frameworks to scale continuous performance evaluation.
cross-functional rca: partner closely with architecture, asic, firmware, and software engineering groups to conduct rigorous root cause analysis (rca) and establish performance targets for upcoming pre- and post-silicon platforms.

as a leader in high-performance computing and Machine Learning, we seek a senior hw program manager with technical skills for the networking hw team. this role involves program management of our network adapters and our switch products, contributing to next-gen data centers.
the hw program management team within our networking business division is looking for an experienced program manager to join its' team. the program manager will oversee the planning, execution, and end-to-end tracking of hw activities across various professional functions and organizations. this role will drive planning processes and drive execution of the programs, and will work with executives, managers and engineers within the organization and with all the interfacing organizations, while aligning with corporate's roadmap, priorities and targets.
what you'll be doing:
build, manage, and execute comprehensive long-term programs, including defining timelines, allocating resources, and establishing key milestones.
coordinate across all project stakeholders, including marketing, project management, engineering, and operations, from initial requirements definition through delivery, ensuring alignment with company strategy, commitments, and goals.
drive cross-functional collaboration and accountability, ensuring timely execution of tasks and achievement of key milestones.
proactively identify, assess, and manage risks in a constantly changing environment through effective prioritization. develop innovative solutions to complex problems and collaborate with stakeholders on mitigation strategies.

we seek an exceptional Network Engineer to join the vertical verification group. as a senior engineer, you will contribute to the vertical verification work, concentrating on validating and improving complex ethernet and infiniband systems within our data center and hpc environments.
you will play a key role in testing advanced networking features, building complex customer-like topologies, and ensuring our products meet industry-leading benchmarks of performance, efficiency, and quality. you will collaborate closely with architects, software engineers, and hardware teams across nic, hca, switches, cpus, and gpus in a fast-paced and highly technical environment. this is an outstanding opportunity to join a highly skilled team and contribute significantly to groundbreaking technology!
what you'll be doing:
review architecture, build, and requirements for new networking features across ethernet and infiniband portfolios
compose and build complex testbed topologies that emulate customer environments
implement, run and optimize integration TEST plans including functional, regression, and performance testing
identify, reproduce, and debug issues; work closely with r&d to drive root cause analysis and resolution
collaborate with automation teams
analyze and optimize network performance, latency, and efficiency
provide clear status updates, reports, and insights on system quality and performance.

as a leader in high-performance computing and Machine Learning, we seek a hw program manager with technical skills for hw r&d. this role involves program management of our interconnect products, contributing to next-gen data centers.
as a top supplier of infiniband and ethernet solutions, we offer best-in-class adapter cards, switches, cables, and software to optimize data center performance. we serve markets like high-performance computing, enterprise, data centers, cloud computing, Big Data, and web 2.0. our ethernet solutions benefit industries such as media and entertainment with datastream and tcp/ip acceleration. we are renowned as a desirable employer, attracting talented and forward-thinking individuals. if you're creative and autonomous, we want to hear from you!
what you'll be doing:
build, manage, and implement comprehensive long-term programs, including setting timelines, allocating resources, and setting up progress milestones.
work with engineers from different teams to ensure consistency with company strategy, commitments, and goals.
facilitate teamwork and cooperation among team leaders to ensure accountability on their tasks and deadlines.
capable of foreseeing and handling risks associated with constant change through proper prioritization. come up with innovative solutions to difficult problems, and co-develop solutions and mitigation strategies.

we have continuously reinvented ourselves over two decades. our invention of the gpu in 1999 sparked the growth of the pc gaming market, redefined modern computer graphics, and revolutionized parallel computing. more recently, gpu deep learning ignited modern ai - the next era of computing. we are a learning machine that constantly evolves by adapting to new opportunities that are hard to seek, that only we can pursue, and that matter to the world. this is our life's work, to amplify human creativity and intelligence. make the choice to join us today.
what you'll be doing:
working closely with product design engineers, you'll perform pcb layout of high speed/high-density value-conscious pcbs for all business units at the company (gpu desktop, notebook, automotive, professional, data center, deep learning, and ai), all using cadence pcb design tools.
focus will be on the complete development of cad layout from symbol creation, floor planning, and detailed component placement, constraints management, with a concept of topology and signal/trace integrity.
you will be responsible for the design releases required generation of artwork files, odb++, and electronic pcb documentation.
your designs will need to follow si constraints, emi/rfi control and fcc, ul and european regulations, ipc specifications and nrc regulations.

we are looking for a talented experienced firmware engineer to join our network adapter firmware team. the firmware team develops cutting edge networking features for cloud, hpc and Storage. we drive the data growth of the world's biggest companies. with talented engineers around the globe, the work environment is dynamic, meaningful and fast paced.
what you will be doing:
work closely with the architecture and different software design teams.
implement new features in the core of our nic firmware.
implement verifiers for advanced features in our advanced random firmware testing environment.
gain a deep understanding of system debug, networking technology and stacks, as well as the hw/fw/sw relationship.
you will learn how a big software project is operated, maintained, qualified and released, and how hardware and firmware are developed.

we are looking for a fuse configuration engineer to join the ic product organization and support fuse configuration across our networking products. in this hands-on engineering role, you will define, implement, validate, and maintain fuse configurations throughout the product lifecycle, from initial definition through mass production and end-of-life.
we are a leading supplier of innovative end-to-end infiniband and ethernet connectivity solutions and services. our portfolio includes adapter cards, switches, cables, and software that deliver industry-leading bandwidth, scalability, and data -center performance.
what you'll be doing:
develop, maintain, and validate fuse configuration files and parameters for multiple ic products.
translate technical requirements from chip design, architecture, q&r, icpe, TEST, and manufacturing teams into production-ready fuse configurations.
perform hands-on configuration updates, technical analysis, troubleshooting, and validation of fuse-related settings.
investigate configuration issues, identify root causes, and implement effective technical solutions.
review fuse change requests and support ccb activities by assessing technical impact, risks, and validation requirements.
develop and improve tools, scripts, checks, and engineering processes that increase configuration accuracy and efficiency.
integrate fuse configurations into product development, validation, TEST, and manufacturing flows while maintaining consistency, version control, and traceability.

we are seeking a physical Verification engineer to help ensure our asic and SOC designs are clean, correct, and ready for tapeout. this role focuses on physical verification quality across layout data, connectivity, and manufacturing rule compliance. you will work closely with physical design, custom layout, and methodology teams to run verification flows, debug issues, and improve signoff robustness. this is an excellent opportunity for an engineer who enjoys detailed analysis and high-impact signoff work.
what you'll be doing:
run and analyze physical verification checks such as drc, lvs, and other tapeout-quality signoff checks.
debug physical verification violations and partner with design teams to drive clean closure.
review layout, netlist, and runset interactions to identify root causes and recommend fixes.
support full-chip and block-level verification readiness across implementation milestones.
improve physical verification flow quality, turnaround time, and automation.
collaborate with methodology, cad, and foundry-facing teams on rule interpretation and signoff quality.

we are looking for a senior software engineer to join the doca sdk verification team. the doca sdk enables developers to rapidly create applications and services on top of our bluefield data processing units (dpus), leveraging industry-standard apis. with doca, developers can deliver breakthrough networking, security, and Storage performance by harnessing the power of our dpus.
what you will be doing:
as a senior software engineer in the doca verification team, you will play a key role in designing and developing the verification infrastructure for the doca platform. this infrastructure is a complex system that executes thousands of tests every night across multiple hardware platforms and configurations. it includes mechanisms for error handling and fault recovery, while TEST results are stored, analyzed using advanced tools, and presented through live dashboards and reports. your expertise in building robust and efficient verification systems will be critical to ensuring the reliability and quality of our software.

we are looking for a talented, fast learner, and highly motivated chip design - Verification engineer. as a member of our chip design team, you will be responsible for verifying portions of the design, of a high performance and low power chip, focusing on such tasks as micro-architectural understanding, verification environment coding and logic debug. this position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines roadmap. we have crafted a team of extraordinary people, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
what you'll be doing:
as a member of our chip design team, you'll own and be responsible for crafting and timely delivery of a verification components and quality of chip design related logic. day to day tasks include:
understand and analyze uarch definitions.
implement verification components to verify rtl meets specifications.
collaborate with our rtl, arch and uarch teams.
work on logic related to switch design.

as a physical layer firmware architecture engineer you will undertake an outstanding role to build the future of computer graphics, ai, and high-speed communication protocols. you will direct ambitious projects across teams and translate customer needs into flawless technical specifications for firmware architecture, system Embedded software, user interfaces, and high-level development.
what you will be doing:
lead projects across team, starting from processing requirements and definitions from customers and translating those into detailed technical specification for firmware architecture, system Embedded software, user interface and high-level design.
supervise the implementation of projects by team-leaders / developers / QA, participate in low level design reviews, QA TEST plans reviews, and keep track of changes and handle obstacles.
define the architecture of implementing physical layer standards into our asic devices.
involved in standard bodies activities and definition of next generation protocols.
define features for the phy layer, to exploit interoperability between different generations of communication.
be involved in product definition and the high-speed protocols that the networking devices will support.
work closely with multi-functional teams - design, backend, system, marketing, firmware, driver, etc. provide architecture definitions and as a result converge on key design decisions.
 
this role provides an opportunity to collaborate with top-tier talent and join a group committed to expanding the limits of what can be achieved. your efforts will have a direct impact on our capacity to compete and lead in the technology sector. join us and bring innovative solutions to life that shape the future of computing!

we are now looking for a senior hpc site reliability engineer to join our mission and continue improving our hpc infrastructure. a meaningful part of our strength is our unique and advanced development tools and environments that enable our incredible pace of innovation. we are looking for architects to help us evolve the way our private compute cloud is architected and optimized.
what you will be doing:
provide leadership in the design and implementation of our large-scale compute cloud that enables the world's top chip modelers, designers, and deep learning experts to invent groundbreaking technology.
identify architectural changes or completely innovative approaches in our cloud architecture and design.
help with strategic challenges we encounter, including: effective resource utilization in a heterogeneous compute environment, evolving our private/public cloud strategy, capacity modeling, and planning for multi-year growth and scaling across our global computing environment!