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We are seeking a highly motivated Chip Architect to join our team and help shape the future of next-generation high-performance networking. our companys next-generation Ethernet and NVL switches are at the core of the worlds most advanced compute clusters from powering AI factories to scaling NVL-based GPU systems used in training/inferencing of the largest foundation models. As a Chip Architect at our company, you will play a central role in defining the architecture of these high-bandwidth, low-latency switches. Your work will directly impact how AI supercomputers, hyperscale data centers, and cutting-edge research platforms communicate at scale. You will join a team with a strong track record of first-in-the-world products and help deliver the next leap in networking technology.
What You'll Be Doing:
Define the end-to-end architecture and full feature set of next-generation NVL and Ethernet switch chips across all stages of the product lifecycle from early concept to deployment.
Develop architectural specifications and design guidelines, and drive trade-off analyses across multiple architecture options.
Lead research and exploration of future architectures, including innovation that contributes to patent development.
Collaborate closely with cross-functional teams including other architecture groups, logic design, firmware, system software, and research to ensure successful execution and integration.
Act as a technical leader and subject matter expert, mentoring others and driving architectural excellence across the organization.

Our networking insights architecture group is looking for a motivated switch performance modeling architect to develop a cycle accurate network simulator with the purpose of analyzing and improving switch performance, used in AI and High-Performance Computing workloads. You will solve complex problems and develop innovative software and hardware solutions using a simulation tool, and be instrumental in determining the architecture of our next generation networking solutions.
What you'll be doing:
Develop cycle-level simulation components to evaluate and analyze micro-architecture and architectural solutions.
Focus on nvlink and spectrum switch hardware modeling, for better performance and optimizations
Analyze and model the communication patterns of key applications.
Explore innovative ideas to improve our systems performance.

our companys Product Engineering group is looking for a well experienced Test architect to join our family and be a part of System Product Engineering. The System Product Engineering team is responsible to assure that our companys customers will get the best state of the art high-quality products.
The teams are involving and part of the full product lifecycle from architecture definition trough development till the product will be EOL (end of life). As part of the effort mentioned above, we are looking for an Electronic Engineer to join the System Design Testing Architecture team and lead Systems HW testability definition for our companys Networking systems.
What youll be doing:
Leading optimal products testing definitions includes: HW, SW, FW, Mechanical fixtures, and cables/harnesses for customized production testing set ups.
Making pitches in front of large audience a new product testing architecture, DFT and testing method while providing justifications for the testing concept.
Responsible for product testing maximum coverage, Testing specification documents and production test flow process for each system
Working with Companys engineering team during the developing process of the product from pre-design trough the design and influence on the product design from DFT design for testability aspects.
Supporting production ramp up and scalability, lead and fast responding time for ECR/ECO implications.
Examine New Technologies, testing capabilities and their implementation for the next generation products
Ensure testing set ups and coverage are met the DFT requirements and timetable
Lead DFT Risk assessment and drive mitigations to reduce the risks.
Working closely with variety of teams: R&D, HW and SW, Chip design, Operations, thermal, signal integrity, FW and SW, layout, and more
The position combines understanding of HW, SW, system manufacturing processes.

We are now looking for a AI Networking Chip Security Architect we are looking for an outstanding security architect with Networking focus to design, validate, and guide implementation of secure architecture of its core products. The candidate is expected to: define problems & deliver highly innovative solutions that lead to significant differentiation in the industry, translate customer needs into architectural, technical & strategic direction, and help to resolve objectives & long-range goals of the Security organization. Leaders in this role will help reduce risk, threats, and vulnerabilities and design new security technologies in our company networking products.
What youll be doing:
Own the security requirements for next gen networking chips in a verity of product lines.
Lead new security technologies definitions into the roadmap of our company Networking devices.
Work with technical and senior leadership staff to turn business directives into functional implementations.
Collaborate between multiple business units and development groups to ensure robust, secure service posture from design to implementation.
Provide hands-on security engineering expertise across a wide variety of platforms.
This role extends across multiple groups and excellent working knowledge in the following areas of expertise is necessary for success:
Chip Security Architecture
Embedded System Architecture and Design
Security around interconnects and protocols
Security Standards
Cryptography.

We are seeking a highly motivated Chip Architect to join our team and help shape the future of next-generation high-performance networking. our companys next-generation Ethernet and NVL switches are at the core of the worlds most advanced compute clusters from powering AI factories to scaling NVL-based GPU systems used in training/inferencing of the largest foundation models. As a Chip Architect at our company, you will play a central role in defining the architecture of these high-bandwidth, low-latency switches. Your work will directly impact how AI supercomputers, hyperscale data centers, and cutting-edge research platforms communicate at scale. You will join a team with a strong track record of first-in-the-world products and help deliver the next leap in networking technology.
What You'll Be Doing:
Define the end-to-end architecture and full feature set of next-generation NVL and Ethernet switch chips across all stages of the product lifecycle from early concept to deployment.
Develop architectural specifications and design guidelines, and drive trade-off analyses across multiple architecture options.
Lead research and exploration of future architectures, including innovation that contributes to patent development.
Collaborate closely with cross-functional teams including other architecture groups, logic design, firmware, system software, and research to ensure successful execution and integration.
Act as a technical leader and subject matter expert, mentoring others and driving architectural excellence across the organization.

Our technology has no boundaries! we are building the worlds most groundbreaking and state of the art accelerated compute platforms for the world to use. Its because of our work that scientists, researchers and engineers can advance their ideas. We pioneered a supercharged form of computing loved by the fastest paced computer users in the world - scientists, designers, artists, and gamers.
We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation Infiniband and NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect at our company, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.
What youll be doing:
Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.
Developing models for simulations and performance testing, analysing the results and development of future HW and SW.
Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are currently seeking a Senior Silicon Security Architect.
we are seeking a technical leader interested in defining, crafting, implementing, and guiding the implementation of security research, architecture, implementation, and design for next-generation our company Networking products. You'll be expected to take a strong hands-on role, working with diverse teams across our company and with external partners to meet security requirements for our state-of-the-art network products.
What you'll be doing:
Research, design, develop and implement architecture solutions (Hardware and software) meeting internal and external security requirements and standards.
Apply innovative hardware security primitives to enable next generation secure software extensions supported by hardware.
Collaborate with partners on the implementation of open-source software.
Collaborate across the company to guide the direction of Silicon security, TEE, working with hardware, software, research and product teams.
Architectural modeling, validation, microarchitectural definition, following standards bodies, and developing infrastructure enabling trusted platforms using hardware security methods.
Work with customers, partners to identify and address security issues and threats.

our companys Product Engineering group is looking for a well experienced Test architect to join our family and be a part of System Product Engineering. The System Product Engineering team is responsible to assure that our companys customers will get the best state of the art high-quality products using the below:
Development and deployment of automatic testers for our companys network business units (Computing network adapters and High-speed switch systems) including hardware and software
Analyzing and monitoring the manufacturing data and find / prevent quality issues based on big data using Machine learning, statistical tools, and AI (artificial intelligence)
Leading smooth production and capacity enlargement
Failure analysis of return material from customers to understand the reason of failures.
Validate the test performance and stability using QA (V&V validation and verification) methods
The teams are involving and part of the full product lifecycle from architecture definition trough development till the product will be EOL (end of life). As part of the effort mentioned above, we are looking for an Electronic Engineer to join the System Design Testing Architecture team and lead Systems HW testability definition for our company's Networking systems.
What youll be doing:
Leading optimal products testing definitions includes: HW, SW, FW, Mechanical fixtures, and cables/harnesses for customized production testing set ups.
Making pitches in front of large audience a new product testing architecture, DFT and testing method while providing justifications for the testing concept.
Responsible for product testing maximum coverage, Testing specification documents and production test flow process for each system
Working with Companys engineering team during the developing process of the product from pre-design trough the design and influence on the product design from DFT design for testability aspects.
Supporting production ramp up and scalability, lead and fast responding time for ECR/ECO implications.
Examine New Technologies, testing capabilities and their implementation for the next generation products
Ensure testing set ups and coverage are met the DFT requirements and timetable
Lead DFT Risk assessment and drive mitigations to reduce the risks.

our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
we are looking for a hardware architecture engineer to join the hardware team! hardware team responsible for full execution of systems ,adapters and interconnect for AI cluster deployments.
What you'll be doing:
Lead hardware next generation end-to-end definition and architecture (Switch, interconnect, adapter)
Define form factor selection; SI, power and thermal consideration, and channel optimization (Mech/thermal/cluster layout)
Align hardware systems and chip design teams toward unified definition
Combine understanding of hardware end-to-end in parallel with Software aspects
The position requires working closely with different Engineering and Operations teams
Looking for a Hands On Eng who is familiar with new technologies and can take a task from scratch to cocompletion with ease!

With the growing demand for traffic bandwidth in datacenters, efficient physical high-speed communication becomes a crucial part of the development of silicon ASCs that serve networking infrastructures. We are looking for a PHY (Physical Layer) Architect for our Architecture team. We are positioning you to a key role to face this challenge and become part of our team, so we can continue developing the best devices in the industry.
our company's networking architecture group is seeking for a highly skilled, leading engineer to explore, and define the Physical layer of our products. As a lead engineer, you'll be responsible to define and drive features and have responsibility on the Physical layer architecture. The role will include definition of both the hardware features and the firmware/software that is involved in operating the physical layer communication, with emphasis on the former. We are searching for hardworking, enthusiastic, engineer which has both highly technical skills as well as good personal skills, in order to be able to lead cross groups activities.
What you will be doing:
Lead projects across team, starting from processing requirements and definitions from customers and translating those into detailed technical specification for firmware architecture, system embedded software, user interface and high-level design.
Supervise the implementation of projects by team-leaders / developers / QA, participate in low level design reviews, QA test plans reviews, and keep track of changes and handle obstacles.
Define the architecture of implementing physical layer standards into our company's ASIC devices.
Involved in standard bodies activities and definition of next generation protocols.
Define features for the phy layer, to exploit interoperability between different generations of communication.
Be involved in product definition and the high-speed protocols that the our company networking devices will support.
Work closely with multi-functional teams - design, backend, system, marketing, firmware, driver, etc. Provide architecture definitions and as a result converge on key design decisions.
Become focal point for our ccompanys physical layer networking communication devices.