our company networking is a world-leader in building the most powerful supercomputers in the world which drive the AI and HPC industry. These rely on high performant network ASICs which connect GPUs at scale for efficient data transfer and compute.
We are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. The role is cross-disciplinary, collaborating with hardware and software teams across the wider our company.
You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.
What you'll be doing:
Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options for our next generation of switches.
Learn and understand the switch ASIC across all performance related aspects
Focus on switch hardware modeling.
Analyze and model the communication patterns of key DL, GAI inference and training applications.
Explore innovative ideas to improve and optimize our chip systems performance.
Requirements: BSc/MSc in Electrical Engineering, Computer Science from a known university.
Experience in developing simulation models.
2+ years of experience in C++ and Python.
Strong debug skills.
Excellent verbal and written communication skills.
Ways to stand out from the crowd:
Master's degree in Electrical Engineering, Computer Science or related technical field.
5+ years of relevant practical experience.
Experience with network simulation tools (omnet, ns3, sst, gem5)
Demonstrated ability to innovate and lead new technologies leading to product impact.
Experience with NVLink/Ethernet/IB technologies.
This position is open to all candidates.