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2 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch and gpu technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies that are in the heart of th ai revolution. our team delivers world class chips solutions for hpc, ai infrastructures, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of nvidia's core technology.
you will take part in the ai revolution led by nvidia, working on cutting edge architecture.
Requirements:
what we need to see:
bsc in electrical/computer engineering or msc in mathematics
5+ years of relevant experience in chip design field (design/verification/formal).
excellent analytical, logical reasoning and problem-solving skills
strong debugging and analytical skills.
strong communication and interpersonal skills are required
ways to stand out from the crowd:
formal verification work experience.
This position is open to all candidates.
 
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2 ימים
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies. our switch team delivers world class bridge and router solutions for hpc, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of core technology.
you will work on developing new formal verification methodologies and tactics.
Requirements:
what we need to see:
bsc in electrical/computer engineering or msc in mathematics.
1+ years of experience
excellent analytical, logical reasoning and problem-solving skills.
strong debugging and analytical skills.
strong communication and interpersonal skills are required.
ways to stand out from the crowd:
formal verification work experience.
knowledge of digital logic.
This position is open to all candidates.
 
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19/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a Formal Verification Engineer for our Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking Switch technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our Switch team delivers world class Bridge and router solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver smart and high bandwidth multi port switches. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:

In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.

You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.

You will work on developing new formal verification methodologies and tactics.
Requirements:
What we need to see:

BSc in Electrical/Computer Engineering or MSc in Mathematics.

1+ years of experience

Excellent analytical, logical reasoning and problem-solving skills.

Strong debugging and analytical skills.

Strong communication and interpersonal skills are required.

Ways to stand out from the crowd:

Formal verification work experience.

Knowledge of digital logic.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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2 ימים
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are now looking for a formal verification manager to join our networking team!
as a formal verification manager in networking business unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of cutting-edge network products and gpu technologies.
this is a unique opportunity to make a real impact at the heart of ai and hpc revolution, while working in a fast-paced, innovative environment.
you will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of formal Verification engineers focused on pre-silicon formal verification of complex digital designs.
define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.
Requirements:
bsc or msc in electrical/computer engineering, Computer Science, or mathematics.
5+ years of managerial experience in a chip design or verification domain.
8+ years of overall industry experience in formal verification, functional verification, or rtl design.
deep understanding of formal verification concepts, tools, and flows.
excellent leadership, problem-solving, and communication skills.
strong analytical and debugging abilities.
ways to stand out from the crowd:
hands-on experience with formal verification
background in developing formal testbenches, assertions, and coverage models.
managerial experience in chip design domain
a passion for recruiting, leading, mentoring engineers and building strong, collaborative teams.
This position is open to all candidates.
 
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2 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
what we need to see:
bsc. in electrical engineering or computer engineering, or equivalent experience.
5+ years of practical verification experience.
experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, verilog, debug tools like simvision/debussy).
experience with Specman is a plus.
good understanding of rtl design (verilog).
strong debugging, problem solving and analytical skills.
excellent communication and social skills.
ability to work in a geographically diverse team environment.
self motivated, independent and target oriented.
This position is open to all candidates.
 
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2 ימים
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we have been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world.
the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. thesystem -on-chip ( SOC ) group is seeking a top SOC Verification engineer to verify the design and implementation of the worlds leading networking socs. in this position, you will get the opportunity to craft complex networking chips and interact directly with architects, designers, and software engineers across sites. this is your chance to shape the future of computing with a world-class team! as an SOC Verification engineer, you will verify the design and implementation of our SOC technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches and nic SOC product lines. we are working closely with a wide range of aspects - chip design, dft, backend, verification and production testing. we are working on the most advanced technologies and complex products. our SOC solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the clock design elements, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our SOC verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
bsc. in electrical engineering or computer engineering.
2+ years of relevant experience.
good understanding of rtl design (verilog)
experience of uvm methodology.
strong debugging, problem solving and analytical skills.
excellent communication and social skills.
ability to work in a geographically diverse team environment.
self motivated, independent and target oriented.
way to stand out from the crowd:
previous experience in SOC and/or verification
experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, verilog, debug tools like simvision/debussy)
background with sv/uvm and Python
This position is open to all candidates.
 
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6 ימים
Location: More than one
Job Type: Full Time
Our Formal Verification (FV) team is seeking a visionary AI Verification Engineer to join our elite Networking Chip Design group. Our team is unique: we define the infrastructure and drive the methodologies for proving the correctness of the worlds most advanced AI and networking architectures. We operate at the cutting edge, leveraging a sophisticated ecosystem of proprietary in-house formal tools and industry-leading vendor EDA solutions.

In this role, you will be a key architect in our "AI-for-FV" evolution. You will work in close collaboration with our internal CAD and Design Technology AI teams to enhance our in-house toolset with artificial intelligence. You won't just be using tools; you will be building the "brains" that sit on top of them-utilizing LLMs and Machine Learning to automate intent-to-proof workflows and debug complex chips with unprecedented speed.

What Youll Be Doing:

In-House Tool Evolution: Partner closely with internal CAD teams to integrate AI capabilities directly into our proprietary FV infrastructure.

Methodology Architecture: Define and evolve the FV teams specialized methodologies, moving from manual property writing to AI-automated assertions.

Next-Gen Orchestration: Develop and integrate AI agents and ML models that interface with our toolchain to automate "intent-to-assertion" workflows and optimize coverage and convergence.

Intelligent Debugging: Create AI-based debug assistants that analyze formal counter-examples, categorize failures, and autonomously suggest fixes for complex logic problems.

Collaborative Intelligence: Act as the bridge between the FV team, Design Technology AI, and CAD groups to ensure our AI solutions provide end-to-end efficiency from RTL to A0 tapeout.

Leadership & Training: Act as the authority on AI integration, training the broader team on how to leverage "human-in-the-loop" AI tools and automated methodologies.
Requirements:
What We Need to See:

Bachelors or Masters Degree in Electrical Engineering, Computer Science, or equivalent experience.

7+ years of hands-on pre-silicon verification experience, with a strong foundation in Formal Verification (FV).

A perspective geared toward automation and experience, defining or refining complex verification infrastructures.

A desire to redefine traditional "manual" verification workflows using modern software and AI principles.

Ways to Stand Out from the Crowd:

Experience building or deploying AI tools specifically designed for hardware (e.g., LLM-based assertion generation)

Proven track record of collaborating with CAD or tool-development teams to refine internal design flows.
This position is open to all candidates.
 
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2 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
work in a combined design and verification team which develops core units within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, full-chip, fw and post-silicon validation.
your daily work will involve all aspects of design verification: planning, coding, coverage and integration
Requirements:
what we need to see:
b.sc or above in electrical engineering or computer engineering, graduation with high scores.
5+ years of validated experience in chip design dynamic verification.
professional verification experience, knowledge in advanced verification methodologies and tools.
demonstrates deep understanding in design and verification logic.
strong debugging, problem-solving and analytical skills.
a great teammate with strong communication and interpersonal skills.
self-motivated, ability to work independently and drive tasks to completion.
ways to stand out from the crowd:
experience in developing verification environments in Specman.
prior design or verification experience of high-speed interconnects and/or SOC.
knowledge in network flows and protocols.
This position is open to all candidates.
 
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6 ימים
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are now looking for an Arch Simulation Manager to join our Networking team! As a Switch-Arch Simulation Manager in our Networking Business Unit, you will lead a team of highly skilled hardware engineers responsible for verifying the next generation of our cutting-edge Switch products. This is a unique opportunity to make a real impact at the heart of our AI and HPC revolution, while working in a fast-paced, innovative environment. You will be part of a passionate and experienced team using modern approaches to validate the performance requirements for the next generation of our networking products. Your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and storage applications.

What Youll Be Doing:

Lead and grow a team of hardware verification engineers focused on Arch performance validation of complex digital designs.

Collaborate closely with Architecture, Design, DV teams to identify verification needs and drive closure.

Provide technical guidance, mentoring, and support to engineers in the team.

Own the planning and execution of simulation deliverables to ensure high quality and timely tapeouts.
Requirements:
What We Need to See:

BSc or MSc in Electrical/Computer Engineering, or Computer Science.

3+ years of managerial experience in a chip design or verification domain.

8+ overall years of overall industry experience in modeling, hardware verification, or RTL design.

Excellent leadership, problem-solving, and communication skills.

Ways to Stand Out from the Crowd:

Hands-on experience with modeling.

Networking and Switch specifically experience.

Background in developing modeling testbenches, regression environments, and CI/CD workflows

Managerial experience in chip design domain

A passion for recruiting , leading , mentoring engineers and building strong, collaborative teams.
This position is open to all candidates.
 
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
2 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
we are now looking for an arch simulation manager to join our nvidia networking team! as a switch-arch simulation manager in nvidias networking business unit, you will lead a team of highly skilled hardware engineers responsible for verifying the next generation of nvidias cutting-edge switch products. this is a unique opportunity to make a real impact at the heart of nvidias ai and hpc revolution, while working in a fast-paced, innovative environment. you will be part of a passionate and experienced team using modern approaches to validate the performance requirements for the next generation of nvidia networking products. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of hardware Verification engineers focused on arch performance validation of complex digital designs.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of simulation deliverables to ensure high quality and timely tapeouts.
Requirements:
what we need to see:
bsc or msc in electrical/computer engineering, or Computer Science.
3+ years of managerial experience in a chip design or verification domain.
8+ overall years of overall industry experience in modeling, hardware verification, or rtl design.
excellent leadership, problem-solving, and communication skills. 
ways to stand out from the crowd:
hands-on experience with modeling.
networking and switch specifically experience.
background in developing modeling testbenches, regression environments, and ci/cd workflows
managerial experience in chip design domain
a passion for recruiting, leading, mentoring engineers and building strong, collaborative teams.
This position is open to all candidates.
 
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1 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for an experienced dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
 
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
 
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production
Requirements:
5+ years of hands on dft/atpg experience knowledge & technical experience in dft asic design and in atpg tools
strong programming skills in scripting languages
bsc. in electrical engineering or computer engineering
quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
 
ways to stand out from the crowd:
knowledge of dft including scan, bist, on-chip scan compression, fault models, atpg, and fault simulation
experience in mentor testkompress atpg tool and retargeting flow
programming languages: tcl, prl, phyton & Unix shell scripts
experience with ate and silicon bring-up
 
This position is open to all candidates.
 
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