דרושים » הנדסה » Verification engineer

Required Experienced SoC Verification Engineer
Which team will you join?
EyeC VLSI team - a group designing the chips for Radar systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
You will take a central hands-on role in Design Verification.
Define Environment micro-Architect, Implement complex UVM environment, Build vPlan .
Execute coverage implementation.
Be part of external IP verification and Internal custom IP.
Be part of System definition and top-level activity.
Take part in Silicon bring-up.

The Radar VLSI team at EyeC is looking for an experienced Formal Verification Engineer to join us! This is a newly established team with a mission to integrate Formal Verification as a key methodology in Radar projects. Be part of a cutting-edge group designing chips for radar systems in ADAS and autonomous vehicles, where your expertise will have a significant impact.
What will your job look like:
You will verify unique and complex design blocks.
Help determine the Formal strategy and methodology for the team.
Explore new Formal methods and tools.

Required Senior Formal Verification Engineer
The Radar VLSI team is looking for an experienced Formal Verification Engineer to join us! This is a newly established team with a mission to integrate Formal Verification as a key methodology in Radar projects. Be part of a cutting-edge group designing chips for radar systems in ADAS and autonomous vehicles, where your expertise will have a significant impact.
What will your job look like:
You will verify unique and complex design blocks.
Help determine the Formal strategy and methodology for the team.
Explore new Formal methods and tools.

Were looking for a Backend Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

Required Experienced DFT Engineer
The EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.