דרושים » הנדסה » Senior VLSI CAD and AI Automation Engineer

we are seeking an experienced and motivated CAD Engineer to join our CAD development team. We are looking for candidates with a strong hardware background and robust software skills, passionate about advancing the development and application of non-EDA tools for circuit analysis. This role involves deep studies of circuit behavior at both the standard cell (STDCELL) and block levels, and offers the opportunity to collaborate with multiple teams across our company.
What Youll Be Doing:
Develop and maintain CAD solutions for both transistor-level and block-level circuit analysis.
Conduct studies of circuit behavior at both STDCELL and block levels, informing tool development and design improvements.
Work with our company quality teams on transistor-level analysis to enhance circuit reliability and performance.
Work with other company teams to identify, develop, and deploy advanced CAD solutions addressing design challenges.
Engage directly with design projects, leveraging CAD tools to solve and improve complex circuit design challenges.

we are on the lookout for a dedicated and driven Software Engineer to join our dynamic VLSI Design Automation team. This team focuses on the development of VLSI CAD tools and web applications, and is responsible for managing and maintaining high-quality VLSI infrastructure, including compute and storage for the Backend Networking team. We seek a passionate engineer eager to effectively manage compute and storage, develop scripts, automate processes, and create dashboards and applications. Our ideal candidate is someone with experience in VLSI methodologies, data-driven, eager to learn, and possesses strong interpersonal skills.
What youll be doing:
Oversee and optimize compute and storage resources, ensuring operational efficiency and success of VLSI projects. Develop and maintain scripts and automation tools to streamline infrastructure tasks.
Engaging in the entire lifecycle of tool and web application development, which includes backend, frontend, data storage design, UI/UX design, testing, deployment, and maintenance.
Design, implement, and maintain dashboards for monitoring and reporting on infrastructure performance and usage.
Challenge existing VLSI methodologies to have better tools and flows.

We are looking for an exceptional MLOps Team Lead to own, build, and scale the infrastructure and automation that powers state-of-the-art Large Language Models (LLMs) and AI systems.
This is a technical leadership role that blends hands-on engineering with strategic vision. You will define MLOps best practices, build high-performance ML infrastructure, and lead a world-class team working at the intersection of AI research and production-grade ML systems.
You will work closely with LLM Algorithm Researchers, ML Engineers, and Data Scientists to enable fast, scalable, and reliable ML workflows covering everything from distributed training to real-time inference optimization.
If you have deep technical expertise, thrive in high-scale AI environments, and want to lead the next generation of MLOps, we want to hear from you.

we are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.
As a design engineer in the DFT design team at our company, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.
As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The company System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.
Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.
Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.
Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.
Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).
Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.
Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.
Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.
Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.
Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

For over two decades, our company has consistently reinvented itself. Our creation of the GPU in 1999 not only fueled the rise of the PC gaming industry but also transformed modern computer graphics and revolutionized parallel computing. In recent years, our work in GPU deep learning has driven the advancement of modern AI, marking the beginning of a new era in computing. we are a "learning machine" that continually adapts to challenging new opportunitiesones that only we can solve and that have a global impact. This is our mission: to enhance human creativity and intelligence.
We are currently seeking a Power Integrity Engineer. You will collaborate closely with our teams in the USA and India, drawing on extensive knowledge, technologies, and tools. As part of our team, you will contribute to the development of our Ethernet switch physical design product line, supporting the process from concept through design, implementation, verification, and tapeout. If you enjoy working with talented individuals to achieve ambitious goals, our company could be the ideal place for you. Our team is dynamic, working with cutting-edge and unique technology. If youre someone who thrives on challenges, we invite you to join this diverse team and make a significant impact!
What you'll be doing:
Ensuring robust power integrity in physical design to optimize power delivery
Design and optimize physical design solutions for power integrity.
Perform power integrity analysis and mitigation.
Focal point for PI for partitions owners.
Collaborate with hardware and design teams on power delivery strategies.
Utilize tools and flow in advance technology to meet project development.

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AIs Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!
We are looking for a CDC Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
You will play a major role analyzing the design and driving fixes as well as developing, maintaining, and improving our Lint, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) constraints and methodology for our SOCs across block level, cluster level, and/or full chip level.
Responsibility for analyzing and optimizing the CDC and RDC sign-offs.
Develop and maintain key CDC/RDC checks and associated sign-offs for SOCs.
Help in driving frontend and backend assertions needed to support CDC/RDC constraints and assumptions.
Learn and understand the switch u/architecture to support the design and verification teams.

we are hiring a senior, hands-on engineer to lead technical innovation in our Design Verification (DV) automation infrastructure. This role requires a strong design/verification background combined with a proactive approach identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. You will directly influence how verification is performed across our companys next-generation Networking chips, enabling more scalable, efficient, and robust flows for complex ASICs powering the AI revolution.
What you'll be doing:
Lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
Identify key challenges and inefficiencies in current DV methodologies and proactively propose and implement improvements.
Work closely with DV engineers, design teams, and tool developers to ensure solutions are practical and impactful.
Balance innovation with hands-on engagement in daily DV issues keeping a strong connection to real-world challenges and support needs.
Act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for DV automation.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at our company works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
What youll be doing:
You will be in charge of state of the art Design for Test/ATPG flows and implementation
Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.
Inventing and maintaining automation flows that provide the short test time to production.