דרושים » חשמל ואלקטרוניקה » Experienced DFT Engineer

our company's Automated Driving group in Haifa is looking for an experienced SoC Design Engineer for DFT team. This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC. At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating! We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the DFT Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. Creating SoC Level micro architecture definitions, RTL coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Develop and optimize the overall layout of the chip, including partitioning, macro and IP placement, and pin placement.
Design and implement efficient power delivery networks (power grids) to ensure stable power to all parts of the chip.
Develop and validate high-performance, low-power clock networks (Clock Tree Synthesis - CTS) to ensure proper synchronization across the entire chip.
Develop, enhance, and maintain custom scripts (e.g., Tcl, Perl, Python) for automation and improved efficiency.
Conduct extensive design rule checks (DRC) to ensure the layout adheres to manufacturing rules, performing layout versus schematic (LVS) checks to verify that the physical layout matches the logical design.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Collaborate with Architecture, Design, and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies, manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop ATE test modules, DC tests, binning, production flows, and characterization flows.
Develop and validate test programs on ATE platforms for New Product Integration (NPI) in preparation for High Volume Manufacturing (HVM), working with ATE vendors.
Support product sustainability, including volume data analysis of screening and characterization data; test time and yield improvements; test escapees and Return Merchandise Authorizations (RMAs) assessments; failure localization; containment measure implementation; and partnership with design manufacturing, quality, and reliability teams to root cause and implement corrective actions.
Develop tools, flows, and methodologies to continuously improve and automate the testing.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Develop and optimize the overall layout of the chip, including partitioning, macro and IP placement, and pin placement.
Design and implement efficient power delivery networks (power grids) to ensure stable power to all parts of the chip.
Develop and validate high-performance, low-power clock networks Clock Tree Synthesis (CTS) to ensure proper synchronization across the entire chip.
Develop, enhance, and maintain custom scripts (e.g., Tcl, Perl, Python) for automation and improved efficiency.
Conduct extensive Design Rule Checks (DRC) to ensure the layout adheres to manufacturing rules, perform Layout Versus Schematic (LVS) checks to verify that the physical layout matches the logical design.