As an RTL Design Engineer, you would be responsible for one or more functional units of the micro-controller and application processor, while working closely with architecture, verification, modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals.
Understanding the high-level specification and requirements of functional units of micro-controller and application processor products.
Define the Micro-architecture for an unit and developing its RTL, including all design stages.
Collaborate with verification team on the test plan development for the blocks and verification closure.
Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets.
Requirements: An ideal candidate will have at least 10 years of work experience in RTL design, SoC integration, memory controller and interconnect IP design.
Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Minimum Skills and Experience:
Experience with memory sub systems and bus architecture.
Required Skills and Experience :
BS/MS in Electrical and/or Computer Engineering with over 10 years of experience.
Knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI) is a plus.
Experience with Verilog, coupled with design synthesis targeted to achieve specified frequency, power, and area targets.
Processor system knowledge includes basic understanding of SoC systems as well as operating system software is a plus.
Great communication & teamwork skills.
This position is open to all candidates.