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We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

Power the Future with us! SolarEdge (NASDAQ: SEDG), is a global leader in high-performance smart energy technology, with over 3000 employees, offices in 34 countries, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive
The IoE group specializes in making SolarEdge devices smarter and more connected. What You Will Be Doing:
* Develop and design high-quality code following best practices to ensure reliability, maintainability, and scalability.
* Optimize and enhance the performance of existing software components.
* Collaborate with hardware engineers to ensure seamless integration between hardware and software.
* Lead technical discussions, code reviews, and mentor junior engineers.
* Participate in the full software development life cycle including concept, design, development, deployment, and support.
* Leverage cutting-edge AI tools and the latest development features to accelerate development, improve code quality, and drive innovation across the team.
* On the Interface team, you'll develop the core infrastructure handling all communication between the device and external systems — cloud, mobile, and other on-site controllers — deployed across millions of devices worldwide.


Country:
Israel

City:
Herzliya

At Infinidat, a Lenovo company, we empower enterprises and service providers with cutting-edge storage platforms that redefine performance, reliability, and cyber resilience at scale. We are looking for a Tech Lead to join our System Validation & Verification team - someone who combines deep hands-on automation expertise with the leadership skills to drive technical direction, mentor engineers, and own end-to-end quality strategy for a complex, enterprise-grade distributed storage system. This role is centered on test design and development - the ideal candidate is someone whose craft is writing and owning tests for complex product features, and elevating a team to do the same at a high level. If you thrive at the intersection of architecture, code, and quality - and get energized by the challenge of making large-scale systems provably correct - this role is for you.

Responsibilities:

* Lead the technical direction of the automation group: define best practices, set coding standards, and guide architectural decisions for testing methodologies and new feature implementations
* Remain hands-on: actively write, review, and contribute to test code alongside the team, leading by example rather than by title
* Design detailed test plans for new features, and review and approve implementation designs proposed by team members for how those features will be tested
* Engage with R&D and Product from the earliest stages of feature development, providing input on testability, edge cases, and quality requirements before implementation begins
* Design and own test strategies for large, cross-cutting features involving multiple services and components working together
* Mentor and grow team members, conducting code reviews and elevating the team's engineering quality
* Work closely with development, product, and architecture teams to influence design decisions from a quality and testability standpoint
* Drive root cause investigations of complex, hard-to-reproduce issues - race conditions, timing-sensitive failures, and problems that only surface at scale
* Own release sign-off decisions - you'll have the authority to say "not good enough"
* Identify gaps in test coverage across service boundaries and drive initiatives to close them

Imagine what you could do here. , new ideas have a way of becoming extraordinary products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Do you want to join us to help deliver the next groundbreaking Apple products?

As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and run-set development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also, you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies.
Responsibilities
Develop, improve and maintain all aspects of physical verification flow and methodology
Coordinate the effort of validating flows, improving for custom checks and data generation
Work with the design and PD teams to facilitate the chip design process
Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
Collaborate with tool vendors and foundries for PDK performance enhancements

We are looking for a software engineer with strong backend skills, a product mindset, and the curiosity to bring LLM-powered agents into the toolchains and Linux environments where chips are actually designed. Success in this role means owning the agentic infrastructure end-to-end: from the platform our agents run on, to the integrations that let them safely act inside our customers' existing flows.
Description
You will join a growing team of ML and software engineers building GenAI solutions for chip design teams. In this role, you will:

* Architect, build, and operate the agentic infrastructure our team relies on:including LLM orchestration, tool-calling layers, multi-agent workflows, and the services that host them.
* Design and implement software solutions for chip design engineers, translating their workflows into reliable, automated agent-driven systems.
* Integrate our agents and services with existing Linux-based environments, in-house tools developed by the team, and third-party EDA tools.
* Manage agentic and ML workflows in production to ensure performance, high availability, and resource efficiency.
* Deploy and maintain production services, with proactive monitoring to catch quality and infrastructure regressions before they reach users.
* Build automated evaluation frameworks to measure retrieval quality, agent execution, and LLM output accuracy across releases.
* Partner with CAD teams to integrate pipelines and agents into CI/CD, ensuring reliable deployments and safe rollbacks.
* Implement access controls, authentication, and secret-handling practices appropriate for working with sensitive design data.
* Collaborate closely with ML engineers, researchers, and our customer teams.

As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our pre-silicon hardware validation efforts using Cadence Palladium emulation platforms, enabling early system integration and hardware validation. You will work closely with SoC architects, RTL designers, and verification engineers to ensure our designs are thoroughly validated before tape-out. You will help define the processes, methods, and tools for emulation environment development and debug of large complex SoCs.
If you enjoy a fast-paced and ambitious environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply and join us!
Description
Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations.
System-level debug and root cause analysis of complex hardware issues on the emulation platform.
IP-level debug and validation, working closely with IP owners to isolate and resolve design issues.
Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization.
Performance profiling and optimization of emulation models to maximize execution speed.
Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.
Responsibilities
Own and maintain Palladium emulation build flows for SoC and subsystem-level models
Drive debug and triage of emulation model issues, working with RTL designers and verification engineers
Support system-level hardware validation efforts and hardware integration
Develop reusable debug methodologies and collateral to accelerate issue resolution
Optimize emulation model performance through compile tuning, partitioning strategies, and platform configuration
Thoroughly document flows, debug procedures, and best practices
Collaborate with cross-functional teams to define emulation requirements and support prototype hardware validation

We are seeking a highly motivated architect to join our team of experts and take part in shaping the future of high-performance ML / AI computing. Our next-generation Spectrum-X, InfiniBand and NVLink systems will be at the heart of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today. As a system/software architect, you will have the opportunity to work on some of the most innovative technology that is currently driving the world forward.

What youll be doing:

Define the next generations of Spectrum-X, InfiniBand and NVLink SW architecture.

Research of various solutions by defining and running POCs, evaluate SW and HW impact and conveying the solution architecture to the relevant teams. The solutions can span over various layers: from algorithms and high level software to firmware and HW.

Collaborate with multi-functional teams, including other architecture teams, VLSI logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

abra professional services is seeking a Project Manager! We are looking for an experienced Technological Project Manager to lead end-to-end development and implementation of AI solutions within a complex, multi-interface technical environment. This role requires a unique combination of technical and architectural understanding, strong client- and business-facing skills, and the ability to manage and drive development teams and vendors. Key Responsibilities
* Lead technological projects from business requirement identification through definition, architecture, development, testing, deployment, and adoption.
* Translate business needs and objectives into functional/technical specifications and actionable development tasks.
* Drive projects focused on AI technologies, including integrating AI solutions into organizational workflows and legacy/enterprise systems.
* Work closely with system architectures, integrations, APIs, and cross-system interfaces.
* Oversee day-to-day execution in Jira—managing backlogs, sprint planning, task prioritization, dependencies, status updates, and progress tracking.
* Maintain ongoing communication with business owners and clients, managing expectations, requirements, and executive status reporting.
* Motivate and coordinate cross-functional development teams, internal departments, and external vendors to hit deadlines and deliverables.
* Concurrently manage multiple projects and interfaces, proactively identifying risks, bottlenecks, and mitigation strategies.
* Oversee UAT testing, production deployment, and system integration.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.


What you'll be doing:

Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.

We are seeking a highly skilled and modern software engineer to develop and prototype brand new advancements in distributed training and inference using our Spectrum-X AI fabric. This role offers a rare chance to pioneer AI and networking technology, contributing to ground-breaking projects that will define the landscape of large-scale AI systems. Improve AI app-networking connection by refining communication, crafting congestion control, coding NIC firmware, and expanding switch SDK features for enhanced AI factory efficiency. Your work impacts large AI system development, scaling, and speed.

What youll be doing:

Prototype end-to-end solutions to improve distributed training and disaggregated inference performance.

Analyze and optimize communication flows across application, transport, and network layers.

Develop system software spanning communication libraries, drivers, and firmware integrations.

Collaborate with hardware, firmware, and SDK teams to co-design network features.

Validate and integrate prototypes into our AI infrastructure and products.