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We are looking for talented engineers to join the Pre-silicon Verification team and help us technically lead the challenges of the next decade, developing a semiconductor platform based on revolutionary architecture, and taking part in the development of cutting-edge products within a disruptive system architecture.

Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment.

Required Tier 3 Service Engineer
About The Position
Act as the highest level of technical escalation for Tier 1 and Tier 2 service teams, leading the resolution of complex technical issues.
Provide advanced remote technical support to global customers, partners, and field teams, including participation in the on-call rotation for after-hours support.
Lead technical service activities for local customers, including troubleshooting, coordination, issue ownership, and follow-up through resolution.
Collaborate closely with R&D, Quality Assurance, Product, and Operations teams to investigate recurring issues, improve system reliability, and drive effective corrective actions.
Develop, improve, and maintain service documentation, troubleshooting procedures, knowledge articles, and training materials.
Deliver technical training and knowledge transfer sessions to global service teams, distributors, and partners.
Support system validation, software upgrades, service readiness activities, and new product introductions from a service perspective.
Analyze service data, trends, and recurring failure patterns using Salesforce, Excel, BI tools, and other available reporting systems.
Ensure all service activities are performed in compliance with applicable Quality, Regulatory, and Safety standards.

Required BI Analyst
About The Position
Serve as primary point of contact for data analysis initiatives, esp. for Finance and Commercial related data. Gather requirements from stakeholders across the company and translate them into actionable specifications for dashboards and reports.
Design, develop, and maintain reliable and scalable dashboards, visualizations, and data solutions that support decision-making.
Author high-quality design documents for reports and semantic layers.
Establish and enforce robust data governance framework to ensure data integrity, data privacy, and compliance
Partner closely with stakeholders to review data on a regular basis and surface actionable insights.
Lead and mentor business data analysts across multiple units, ensuring consistent methodologies and best practices.
Monitor and improve data quality, resolving discrepancies across reporting systems.
Collaborate with IT, Data Engineering, and business teams to integrate and optimize data sources for reporting solutions.
Stay current with emerging data technologies and methodologies
Promote a data-driven culture by driving analytics literacy and recommending process and tool improvements. Contribute to the data strategy and roadmap.

We are looking for a Manual QA & Integration Engineer to work on complex systems. The role primarily focuses on manual software testing, alongside integration activities in laboratory environments and at customer sites.

During specific periods and according to project needs, integration activities may temporarily become a significant part of the role.

Responsibilities
Performing unit-level and system-level software testing, including test result analysis.
Analyzing requirements, writing test documentation, and conducting test reviews.
Identifying, analyzing, and resolving complex issues in real time.
Reporting defects and performing retesting following their resolution.
Performing end-to-end integrations in laboratory environments and at customer sites, including on-site system implementation.
Leading tasks and collaborating with multiple stakeholders, including development teams, product managers, and customers.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data.
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models.
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages.
Potentially (in the future), lead a team doing above activities.
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

We are forming a new team to explore AI Compilation Boundaries
This team will operate under a unique manner, as described below -
The environment
- Startup-like intensity
Small team
High ownership
High visibility
Merit is the essence, not titles
- Fast pace
Todays state of the art is tomorrows baseline
We aim to go beyond
- Incubator mindset
Take on hard challenges, dismantle, and regroup as novelty
- Elite technical culture
Strong experts
Strong standards
Strong execution.
Ratio beats seniority, not the other way around
- No artificial boundaries
We challenge assumptions, and question constraints, and leave no quarter
- Direct exposure to the latest and greatest AI technology
Real hardware
Real toolchains
Real large-scale AI applications
All pass through and impacted by our work
- First-principles thinking
out-of-the-box is a compromise
Do not accept that a box had to exist in the first place.

In this role, you will be responsible for several teams of architects, engineers and software developers, all working together to conduct state-of-the-art R&D in system and network architecture. As the group lead, you will guide and mentor the individual team leads, and also conduct hands-on work leading architecture, technology innovation and technical planning and of high-performance computing cluster network, which oriented at AI, HPC, and big data.

Responsibilities
You will perform a wide range of duties including:
Architecture Innovation:
Deeply analyzing the advantages and disadvantages of mainstream network systems, to find opportunities for network architecture innovation;
Insight into the technology developing trend of the high-performance computing network field, and leading the corresponding technology planning.
Exploring new architectures of high-performance computing network systems and efficiently integrating communication library, topology, and network protocol to solve performance bottlenecks.
Technical breakthroughs in networking and cluster routing algorithm：
Analyzes computing cluster network performance and leads the development of computing cluster network technologies
Research and optimize the heterogeneous interconnection topology of key computing chips to continuously improve the key competitiveness of Huawei computing heterogeneous chipsets.
Responsible for the research of data center network technologies, and guide network topology design and routing algorithm development
Group leadership:
Lead the development of a comprehensive system architecture for AI Fabric and HPC Fabric solutions.
Manage and mentor highly skilled team leaders, to ensure that the group operates together in pursuit of common goal.
Foster a collaborative and innovative work environment.
Provide technical guidance and support to team members.
Collaborate closely with cross-functional teams internationally, including hardware, software, and ucode design teams, to ensure alignment of architectural decisions with product and platform common objectives.
Initiate and supervise collaborations with top academic researchers in Israel and abroad.
Stay up to date with emerging technologies and industry trends in AI, HPC and big data industries.
Evaluate and recommend technologies and next generation projects.
Occasional travel related to ongoing projects, seminars, conferences etc.

Join a team developing next-generation AI accelerators, working at the intersection of AI algorithms, software, and hardware.

Our team at the Huawei Computing Network Innovation Lab is looking for exceptional talent to join us and lead the development of next-generation data centers. We create cutting-edge technologies that synergize software and hardware in tandem to accelerate compute, storage, and networking at large scale. We aim to drive innovation and deliver software-defined infrastructure and algorithms for HPC, AI/ML, and Big Data applications.
We are looking for an outstanding Research Team Lead with deep hands-on expertise in large-scale distributed systems, AI framework infrastructure, and performance optimization on custom accelerators. If you are a visionary technical leader, a skilled communicator, and a team builder who thrives at the frontier of systems and AI research - you're welcome on board.

What Will You Be Doing?
Lead and grow a world-class team of researchers and engineers working on distributed AI infrastructure and systems software.
Architect and own the software infrastructure enabling distributed training and inference on Huawei's custom accelerator hardware (e.g., Ascend NPU).
Drive research and development on communication libraries, runtime systems, memory management, and graph execution & synchronization at scale.
Optimize end-to-end performance across large-scale clusters, covering both scale-up (multi-device) and scale-out (multi-node) configurations.
Design and implement high-performance communication backends and collective operations (AllReduce, AllGather, broadcast) for distributed training workloads.
Collaborate cross-functionally with hardware architects, compiler teams, and framework engineers to co-design hardware-software solutions.
Publish and present research findings at top international venues (NeurIPS, EuroSys, SC, MLSys, OSDI) and represent the team externally.
Mentor engineers and researchers, conduct performance and growth reviews, and shape team culture and technical direction.
Partner with top academic institutions and open-source communities to advance the state of the art in distributed AI systems.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

*Part-Time or Full-Time Opportunity

In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.

Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system

We are looking for an architect to work on the invention and development of new SW visible CPU technologies to improve performance of SW scenarios related to memory ordering, memory coherency, multithreading, synchronization, memory safety, caching, etc.
The minimal tasks of this role are:
1. Modeling of new memory related architectural features in the existing CPU performance simulator
2. Development of performance tests or adaptation of existing workloads to be suitable for simulation
3. Conducting performance studies for the workloads of choice either in the performance simulator or on a real chip
4. Develop analysis, conclusions and recommendations based on the above activities
The role can comprehend much more than that depending on the skills, talent and experience of the candidate creating a career path over time. For example, to invent new instructions and mechanisms to overcome significant performance bottlenecks in these areas, refinement and further development of ideas provided by others. Possible participation in development in additional domains
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!

Our company is seeking a Hardware Development Team Lead to lead cross-functional development and integration activities across the organization. The successful candidate will oversee collaboration between all engineering disciplines, including Hardware, RF, Software, and Firmware, while serving as the key interface with the Systems Engineering team.
Key Responsibilities:
Lead and directly manage a multidisciplinary engineering team developing complex systems, including Mechanical, Hardware, Firmware, and RF engineers, ensuring execution according to project plans, schedules, and objectives.
Lead end-to-end product development, including system architecture definition, technical oversight, prototype development, and design verification and validation (V&V).
Serve as the primary liaison between development engineers, the Systems Engineering team, and Project Managers.
Evaluate, introduce, and implement new development tools, methodologies, and emerging technologies.
Define priorities and allocate engineering tasks based on business needs, project requirements, and market considerations.
Establish engineering methodologies, development processes, project milestones, and required deliverables for internal design reviews (PDR, CDR, etc.).
Define engineering roles and responsibilities, recruit new team members, mentor engineers, conduct performance evaluations, and develop individualized professional growth plans.
Conduct routine management activities, including status meetings, management reviews, and project progress meetings.
Prepare technical responses for project tenders (RFPs), including technical proposals, effort estimation, and cost evaluation.
Provide technical support for both internal engineering challenges and customer-facing technical issues.
Lead internal and customer design reviews as required.