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our company's Imaging Radar group develops innovative high-performance Radar solutions for ADAS and Autonomous Driving markets. We are seeking an experienced System Architect to join us.
What will your job look like:
Lead End-to-end life cycle of the Radar System-on-Chip architecture definition and development.
Work in close collaboration with the various teams, including system, algo, design, verification, backend, firmware, package and post-silicon.
Provide architectural guidance and tradeoff recommendations throughout the whole design process from concept through production.
Responsible for 3rd party IP technical evaluation and selection.
Manage Interconnect, DSP and CPU definition and optimization.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Participate in the development of flows & methodologies from Synthesis , Place& Route & all signoff flows.
Plan & execute flow releases, coordinate & track development tasks.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new tools features and methodologies to bring innovation with significant RoI.
Hands-on physical design block ownership end to end, from Synthesis floor planning, Place & Route with target to achieve best PPA.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Serve as the technical lead while mentoring and guiding team members.

we are a pioneering force in the autonomous vehicles (AV) industry. Join us to build the brain behind the car a large-scale, multi-task neural network that powers the core of our companys autonomous stack. Youll design and train cutting-edge deep learning models tailored for our custom EyeQ chip, tackling end-to-end challenges and deploying real-world solutions. From novel architectures and advanced training techniques to performance tuning under tight constraints, youll work closely with software and hardware teams to turn research into high-impact, production-ready systems. If youre a brilliant, hands-on researcher with a passion for shaping the future this is your launchpad.
Why us?
Our team is at the forefront of our companys most advanced AI efforts.
As a central hub for deep learning innovation, were trusted with designing the core neural network architecture that powers the companys flagship products.
If youre seeking a high-impact role among top-tier researchers and developers this is the place to be.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Lead the development of flows & methodologies from Synthesis, Place & Route & All signoff flows.
Plan & execute flow releases, coordinate & track development tasks between the team.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Serve as the technical lead while mentoring and guiding team members.

Power the Future with us! a global leader in high-performance smart energy technology, with over 3000 employees, offices in 33 countries, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery Storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive. We are looking for an experienced Analog Design Group Manager to lead and grow our analog design team. The ideal candidate will have deep expertise in complex analog circuit design, including ADCs, acquisition systems, and power management, as well as proven leadership in managing design teams and delivering successful silicon tape-outs. What will you be doing: Lead and mentor a team of analog design engineers in the development of complex mixed-signal and analog ICs.
* Drive architecture, specification, and implementation of analog blocks such as ADCs, acquisition systems, and power circuits.
* Oversee the full design cycle from concept through to tape-out, ensuring high-quality results (including DRC/LVS sign-off).
* Collaborate closely with digital design, verification, layout, and system engineering teams.
* Define methodologies, best practices, and quality standards for analog design within the group.
* Provide technical guidance, training, and career development for team members.

our company's Networking unit has continuously reinvented itself over two decades. Our high-speed products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions. We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. our company'sIC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering and designing state of the art high-speed Interconnect systems for Supercomputers and Datacenters. This position will collaborate with Technical Package Lead and cooperation with different design teams and development of complex, detailed layout of IC substrates for our company's products.
What you'll be doing:
As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.
Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.
Optimize package pin out incorporating system level trade-offs of pins assignment.
Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
In close co-operation with the SI/PI/HW design teams and product teams
Planning, ensuring stakeholder management and leading projects from start to finish.

our company's Autonomous Driving Software Group in Haifa is looking for a Teach Lead to join our Team. Our group is responsible for writing new code to replace the existing code with a new design. We develop the software architecture system and tools to enable support for many new design wins and scale the company project to run efficiently in vehicles contributing to saving lives and enabling autonomous vehicles.
What will your job look like?
You will be part of the design of the car application that controls the main execution flow of various software components running on the company's chip. Additionally, it manages many sensors and their inputs, such as cameras, radar, and car signals.
The application integrates these inputs and feeds them into various algorithms to create a comprehensive worldview for the car.
The project is challenging both in its real-time complexity of a system with multiple sensors and being part of the overall automotive car system architecture.
Provide guidance and mentorship to software development teams.
Defining work process tools and technologies to enforce our customers' requirements.
Working in a large group of software developers with cross-team collaboration.

we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Responsible for chip floorplan and pins placement
Running, debugging and approve Physical verification flows across multiple projects
Perform physical layout planning and optimization.

we are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence.
Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.
Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects.

our company's Autonomous Driving Software Group in Jerusalem is looking for an experienced C++ developer to join our team! Our group is responsible for developing new ethernet switch architecture and tools to replace existing code with a modern, scalable design. We enable support for new design wins and help scale our companys technology to run efficiently in vehicles, contributing to saving lives and enabling autonomous driving.
What will your job look like?
Take part in designing and developing large-scale network applications running on our cutting edge platforms which have our industry leading EyeQ chip.
You will work on a complex real-time system involving multiple sensors as part of a broader automotive system architecture.
The main application is developed in C++ for Linux environments.
You will develop advanced simulation software used company-wide, integrating the latest company's technologies.

Required Product & Test ATE Engineer
About The Position
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ , Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

Join the company Networking business units IC Silicon Product Engineering team and play a critical role in shaping the quality and success of our next-generation DPU/SoC products. Were looking for a driven and versatile engineer to lead system-level testing across the engineering and production lifecycleensuring our products meet the highest standards before they reach our customers.
This is your opportunity to take full ownership of end-to-end validation processes, work with the latest in high-performance network-on-chip technology, and make a direct impact on the quality of our company's cutting-edge silicon products. Youll collaborate with global, cross-functional teams and drive quality decisions that shape our production and product coverage.
What Youll Be Doing:
Lead and own the full system-level test cycle across the production line (from definition to execution)
Drive cross-functional collaboration with hardware, software, marketing, and operations teams worldwide
Extract key product insights from stakeholders and documentation to design robust test plans
Design and execute automated system-level tests that reflect real-world usage scenarios
Analyze test results, pinpoint root causes of IC issues, and effectively communicate findings
Champion production quality and make sure what we ship is top-tier
Contribute to the products success by ensuring reliable coverage and test effectiveness.

we are looking for best-in-class STA (Static Timing analysis) Physical Design Engineers to join our outstanding Networking DFT team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
DFT STA execution, from rtl driven constraints and definitions through DFT constraints quality assurance to STA sign-off.
Be part of a unique team of experts who have deep understanding in all aspects of pre and post silicon.
Be exposed and work on a variety of challenging designs, unique DFT solutions that require deep silicon implementation understanding.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part in flows development.

we are looking for best-in-class STA Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part inflows development.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and verification closure. You will verify digital designs and collaborate with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.