Join a dynamic and innovative team driving the development of state-of-the-art EDA/CAD tools and scalable design automation infrastructure to empower advanced integrated circuit (IC) design. You will design, develop, and maintain next-generation design robust software tools and workflows across all domains in integrated circuit design, while ensuring compatibility with legacy software solutions.
Roles and responsibilities:
Build, maintain, and optimize CAD tools supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate design flows spanning frontend RTL-to-GDSII, digital backend implementation, and physical/verification signoff, ensuring scalability and tapeout readiness.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Design and implement testing frameworks, regression suites, code review practices, and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.
Requirements: B.Sc. in Electrical/Computer Engineering, Computer Science, or Practical Engineering, or equivalent hands-on IC CAD/EDA experience.
Hands-on experience with physical design and verification tools, including both commercial (Cadence, Synopsys, Mentor) and in-house CAD solutions.
Strong programming skills in SKILL, Python, Tcl, Perl, and Shell (Csh, Bash).
Ability to debug, optimize, and troubleshoot CAD flows and physical design workflows.
Familiarity with regression testing, code review, flow validation, and CI/CD practices in CAD/EDA environments.
Strong communication and teamwork skills, and the ability to work independently in a dynamic, fast-paced environment.
Preferred:
Prior experience as a CAD/EDA Engineer or Physical Design Engineer in a semiconductor environment.
Deep understanding of IC physical design and verification flows:
Floorplanning, placement, routing, power, and clock distribution
DRC, LVS, ERC, parasitic extraction
Physical verification and tapeout readiness
Advanced SKILL programming for automation and productivity.
Experience with tapeout preparation, design rule integration, and physical verification.
Knowledge of PCells, parameterized devices, and flow generators.
Proficiency in physical verification, runset programming, and maintenance.
Experience building automated regression environments for CAD/EDA flows.
Experience with in-house CAD tool development and with the integration and customization of both in-house and commercial solutions.
This position is open to all candidates.