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We are looking for talented networking software engineers to develop an innovative new communication stack. Were starting from the ground up, rethinking existing protocols and network accelerators while designing both hardware and software for a new low-latency compute platform. We care about results and insist on doing things right. Our engineers are not siloed into narrow areas; our ideas are cross-fertilized among teams. Our technical backgrounds are diverse and we don't have preconceived approaches or cookbooks, so come and invent! The hardware teams are just a few steps away and really like hearing our ideas. This is a unique opportunity to develop creative solutions from concept to implementation.
Responsibilities
Take part in developing a networking stack from the ground up:
Analyze customer applications and explore creative ways to accelerate them in hardware or software
Find the best ways to process packets on NextSilicons hardware platform
Participate in architecture of future NextSilicon NIC generations
Develop user-space libraries and benchmarks for low-latency communication
Work closely with the hardware teams to offload key features into the next generation of products.

We are seeking a talented engineer to work on our AI software stack-specifically, the low-level optimization of AI models and kernels for our unique hardware architecture.
Responsibilities
Develop our optimized AI libraries and related components in the SW stack.
Drive the performance optimization of AI models running on our unique architecture.

Our team is looking for a skilled professional to join the AI software group. In this role, you will focus on our AI kernel compilers, ensuring our hardware delivers peak optimization for sophisticated and custom AI kernels. You will work extensively with various kernel infrastructures, including Triton and CUDA, while collaborating closely with our AI graph compiler teams.
Responsibilities
Develop our AI kernel compilers and related components in the SW stack.
Drive the performance optimization of AI models running on our unique architecture.

We are seeking a top notch software engineer to drive forward the development of the full software stack and architecture behind our revolutionary coprocessor. You will demonstrate creative and critical thinking capabilities and have a genuine passion for tackling complex low-level software issues.
As part of the memory system team, you will work on design and implementation of new and enhanced features of the memory system to support high performance computing and AI applications in the Maverick accelerator runtime environment.
You will work closely with software engineers, hardware engineers, compiler developers and other stakeholders to enable the most efficient execution of applications on a large scale, multi threaded and highly distributed system across multiple disciplines with a deep OS Internals point of view.
Responsibilities
Work on design and implementation of new and enhanced features of the memory system for the Maverick accelerator
Develop a high performance, low latency distributed unified virtual memory management system
Work on system software support for the next generation Maverick system
Define feature development scope and plan for successful product delivery.
Wide system impact through collaboration with software engineers, hardware engineers, compiler developers and other stakeholders.

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.
Responsibilities
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches
Work closely with the verification team to ensure the quality of the product
Build and maintain a smart and scalable verification environment that ties into various systems
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design.

We are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of Nextsilison BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.
Responsibilities
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet timing, area, and power constraints
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip integration.

We are looking for a talented and experienced engineer to participate in designing the next era of computer architecture. In this position you will take part in designing the critical parts of our future chips. You will transform architectural requirements to micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.
Everything we do is guided by three core values:
Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.
Responsibilities
Define and drive the design of advanced blocks from micro-architecture phase to netlist
Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts
Leading processes relating to power optimization
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making.

Required Physical Design Team Leader
Description
We are reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. We have developed a novel software-defined hardware architecture that is achieving significant advancements in both the HPC and AI domains.
Everything we do is guided by three core values:
Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.
Come help lead the design and development of one of the most ambitious products at the forefront of compute technology!
Responsibilities
Lead a physical design team responsible for all stages of the physical design process-floor planning, placement, clock tree synthesis, routing, timing, and power optimization at both block and subsystem levels.
Mentor and guide a team of physical design engineers through all stages of the design flow.
Collaborate closely with project managers and other technical leads to ensure timely delivery and successful completion of projects.
Drive the technical direction of the physical design process to ensure efficient, high-quality outcomes.
Develop and implement best practices for physical design and continuous improvements of design workflows.
Optimize designs for performance, power, and area (PPA) to meet project goals.
Ensure compliance with DRC (design rule checking) and LVS (layout versus schematic) requirements. .
Drive timing analysis and closure, working closely with the RTL design team to resolve timing violations.

We are looking for a talented and experienced design manager to drive and help our group to get to the next era of computer architecture. In this position, you will design the critical parts of our future chips. You will be involved in the full design cycle from architectural requirements into micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.
Responsibilities
Be accountable for your team's milestones & timelines
Leading your team members and developing their abilities
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators, monitor and report execution progress to enable prioritization and clear decision-making
Acquire the system Architecture and be part of the leading technical FE forum.

We are looking for a talented and experienced engineer to take part in the Emulation and Prototyping efforts for the companys core product. This position involves building a complex emulation environment from scratch, and collaborating with software, design, and verification teams. In this role, you will be leading emulation from A to Z and will have a critical impact on the company.
Responsibilities
Develop and build complex emulation models for coming generations of accelerators, including transactors like PCIe, SPI, and embedded CPUs
Work with the software, design, development, and verification teams to understand the functional and performance goals of the products design
Optimize the model for speed and capacity and develop debug abilities to support software and firmware teams
Work with software design and development teams to define and develop BFM, test bench, and checker tools
Review specifications and develop attributes, tests, and coverage plans for the emulation system.

Required System QA Engineer
Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment - those who want to be part of the next generation of airspace security innovation.
Join us and help make the world a safer place.
Work with the worlds leading cyber-takeover counter-drone technology provider and shape the future of safe airspace.
The Mission:
Your role is to ensure the operational stability and resilience of the Applications Ecosystem, encompassing National C2, MSC2, and Edge C2 platforms. You will rigorously test the seams where these distributed systems integrate. You are expected to execute with precision, learn the architecture deeply from the ground up, and evolve into the Domain Expert
for our multi-tiered command and control system. Critically, you will champion a "Shift-Left" quality approach: preventing defects during the design and planning phases rather than merely catching them after development is complete.
Core Responsibilities
Actively participate in Product Requirements(PRD), High-Level (HLD) reviews to enforce system testability before code is written.
Execute and automate comprehensive test plans across Edge C2 nodes, MSC2 instances, and National C2 cloud environments.
Validate complex data flows and state synchronization across geographically distributed components.
Simulate degraded network conditions, forced disconnects, and VPN tunnel collapses to validate system recovery and data integrity.
Isolate integration breakdowns between Web Applications and backend microservices.
Analyze complex system logs using modern observability tools to provide developers with exact root-cause indicators and precise reproduction steps.
Integrate automated test suites into the CI/CD pipeline to ensure continuous validation.
Maintain clear, artifact-based documentation of test coverage, system behavior, and defect tracking.

RF/HW & System Validation Engineer
Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment - those who want to be part of the next generation of airspace security innovation.
Join us and help make the world a safer place.
Work with the worlds leading cyber-takeover counter-drone technology provider and shape the future of safe airspace.
Scope:
As an RF/HW Validation Engineer, you will bridge the gap between HW & RF validation and complex system-level testing. You will design, develop, and execute automated and manual test plans to verify the performance, reliability, and compliance of our SDR (Software Defined Radio) architectures and multi-layered tactical systems (including integration with other systems).
Key Responsibilities:
System-Level Testing: Execute end-to-end system testing of counter-drone platforms, verifying the integration of RF hardware, firmware, and complex software-defined radio algorithms under real-world scenarios.
Hardware Product Testing: Test and validate various HW products, including antennas, radar systems, jammers, and related peripherals.
Failure Analysis & Troubleshooting: Debug complex RF anomalies, signal integrity issues, and system bugs down to the component/board level, working closely with RF Design, Board Design, and SW teams.
Documentation: Create comprehensive test plans (ATP/DTP), write test reports, and present data-driven analysis to cross-functional R&D teams to impact the next generation of hardware.

We are looking for an experienced system engineer to participate and lead the development of a radio-based drone detection and mitigation system as part of the company products.
Responsibilities:
Lead features and platforms from ideas to releases.
Guide and participate in the research and analysis of both proprietary and standard radio communication
protocols.
Develop and optimize algorithms for scanning, signal separation, antenna selection, etc.
Define requirements and guide other multi-disciplinary teams (SW, Modem algorithms, DSP, and FPGA) through
implementation and debugging.
Analyze and define complex system behaviors, state machines, algorithms, and event-response logic, including
radio link budget considerations.
Perform independent, hands-on debugging and optimization for system problem-solving using tools like
MATLAB, Python, Excel, and other log analysis software.
Gain a deep understanding of the full system to guide and support development, testing and validation teams.

We are looking for a talented Communication PHY Research Engineer to join our
growing, highly motivated, and skilled modem research team, to lead and participate in
research of proprietary wireless communication signals and design modulators,
demodulators as part of our counter-drone cyber-based product.
Responsibilities:
Research and analysis of proprietary air interface: algorithm research of sampled wireless signals using MATLAB or Python, to define all radio characteristics including sample rate, modulation scheme, error corrections, spreading techniques and more.
Full modem implementation and simulation in MATLAB or Python.
Analysis of protocol behavior and performance improvements.
Proposing and developing algorithmic approaches to address technical challenges and complex problems.
Technical subject matter expert (SME) for communication protocols, providing support and consultation on R&D-related challenges and issues.