Performs comprehensive simulations and validations to generate Intel design guidelines to guide system -level power integrity design including, but not limited to, Silicon, package, socket, boards, and voltage regulators.
Performs AC and transient simulation to provide impedance profile of the whole power delivery path, from the VR to the motherboard, the package and the die.
Perform time domain analysis in HSPICE, ADS to find noise levels in I/O rails.
Provides guidance to the design team on capacitor numbers values and power plane shape width.
Correlating simulations with system measurements.
Deliver optimized PI solution meeting the product performance
Provides DC and resistance simulation to provide Rpath from the VR to the package pins, voltage drop, current density and power loss analysis.
Requirements: Candidate must possess a bachelors degree or higher in Electrical or Electronic Engineering or Ph.D. in a power integrity engineering related area.
10-12 years of experience in Silicon, package board level power integrity design.
Solid understanding of theory on power integrity as well as having applied it to actual designs in the industry or in the academy.
Knowledge and understanding of how power integrity on die, package, and board affect bit error rate of serial and parallel interfaces, such as high-speed serial channels (i.e., 56G/112G PAM4 and beyond, PCIe Gen4/5/6, etc.) and DDR4/DDR5 memories.
Power Integrity simulation software use such as Sigrity PowerSI, PowerDC, HSpice and Matlab.
Package/board routing CAD tools such as Cadence Allegro and Mentor Graphics.
Hands-on experience with lab equipment for correlation
This position is open to all candidates.
