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Required Physical Design Engineer, SoC Static Timing Analysis
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. In this role, you will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Drive the sign-off timing convergence for high-performance designs.
Set up the timing constraints, define the overall static timing analysis (STA) methodology, set up the STA infrastructure and sign-off convergence flows, and work closely with block owners throughout the project for sign-off timing convergence.
Work with logic designers to drive architectural feasibility studies, develop timing, and explore RTL/design trade-offs for physical design closure.

Required Junior SoC IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our Platforms Infrastructure Engineering team designs and builds the
hardware and software technologies that power all of our services. Our computational challenges are complex and unique, enabled by custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concepts all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers, affecting millions of users.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Required Senior SOC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Required Senior SoC Hardware Quality and Reliability Engineer
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Own technical specifications, architectural definitions, and physical power-on of custom qualification vehicles (HTOL load boards, ESD fixtures, latch-up rigs). Drive external layout vendors to achieve seamless electrical correlation with ATE environments.
Govern execution quality of applied stresses, define electrical, thermal, and telemetry parameters on test vehicles to ensure uniform, valid stress profiles without unintended overstress or setup artifacts.
Lead the end-to-end engineering delivery lifecycle for qualification hardware, map and drive critical cross-functional dependencies across internal validation and product engineering teams to ensure on-time readiness.
Serve as the primary technical interface for external PCB layout houses, fabrication shops, and component suppliers; manage design reviews, track lead times, and enforce delivery schedules.
Lead laboratory troubleshooting for qualification hardware anomalies; isolate setup/socket faults from true silicon failures and drive supplier corrective actions (CAPA) when board excursions occur.

Required Senior SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Senior SoC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure activities.
Contribute to test plan and coverage analysis of the block and SoC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Required Senior SoC Test Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop ATE test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Product sustain support, including volume data analysis, test time and yield improvements, assess test escapees and RMAs, localize failures, implement containment measures and partner with design, manufacturing, quality and reliability teams to root cause and implement corrective actions.
Develop tools, flows and methodologies to continuously improve and automate the testing life cycle.

As Senior System Engineer you will have significant impact on our multi-disciplinary R&D projects, grow with us as we venture into new technologies and will lead work groups in our projects as part of the connected devices line of products during the product lifecycle of both discovery and delivery.

The responsibilities will include defining System, HW, Embedded, ATE, SW & Integration requirements as well as contributing to the design stage of each discipline, defining the protocol, technical problem solving, proof of concept and field testing and assisting in tests design and investigations.



The position requires multidisciplinary understanding, ability to quickly grasp new technological aspects as well as constraints , the capability to work in a multi-site matrix organization and working closely in a Product and Platform team with other system engineers, embedded software developers, HW engineers, Integration Engineers as well as backend and front-end teams.

We support farmers by providing real-time actionable information to help them manage their herds. It provides pet owners with smart devices and data that give them a better understanding of their pet's activity and health needs, enriching relationships. It helps conservationists safeguard natural environments and wildlife.

Leveraging decades of Technological Research & Development experience across many markets, technologies, and species, along with development environments and Quality Assurance procedures, we're always inventing new ways to look after the health and well-being of animals. Our decades of experience keep us ahead of the curve by leveraging advanced Technological Solutions from enhancing the precious bond between people and their pets, to advancing animal healthcare and wildlife preservation.

Position Summary
The Technologist is responsible for supporting the transition of products from development to manufacturing and sustaining production throughout the product lifecycle. The role focuses on PCB/PCBA technologies, manufacturing processes, supplier management, DFM/DFT reviews, failure analysis, engineering change implementation, and continuous process improvement.

The company is based in Netanya.

Responsibilities:

Serve as the technical focal point for PCB and PCBA manufacturing technologies.
Work closely with the R&D and Lead DFM, DFA, reviews for new and existing products.
Support NPI activities and production transfer to manufacturing sites.
Review PCB stack-ups, materials, fabrication drawings, Gerber data, and manufacturing documentation.
Work closely with PCB and PCBA suppliers to resolve manufacturing issues and optimize yield.
Support engineering changes (ECO/ECR) and product lifecycle activities.
Lead root cause investigations and corrective actions for production and field failures.
Review and approve manufacturing documentation including INFO files, EQ files, specifications, and work instructions.
Drive continuous improvement initiatives focused on quality, cost, and manufacturability.
Support incoming quality requirements and supplier qualification activities.
Collaborate with R&D, Quality, Operations, , and Manufacturing teams worldwide.
Provide technical guidance regarding PCB technologies, materials, surface finishes, vias, stack-ups, and assembly processes.
Published effectively report results to peers and management
Manage the Spec and requirements of the Battery and NFC

This is an opportunity for you to integrate with end customers in both hands-on and advisory roles to solve technical challenges with various test cell set ups. To work on the bleeding edge of semi-test technology and to sharpen your relationship management skills while developing strategic partnerships that will round out your arsenal of 3rd party vendor provided products that enhance our solutions.

Key Responsibilities:
Influence next generation ATE tester and Test Cell product roadmaps
Work directly with leading edge semiconductor companies supporting their efforts to develop Test Cells to enable advanced chip designs to market
Responsible for the mastering of Teradyne Test Cell products, product applications and policies.
Provide expert advice to customers, Sales, FAEs and support staff while working closely with sales/marketing management and test cell staff to ensure that relevant technical information is promptly and accurately communicated.
Develop strategic relationships throughout our sales team and customer's key technical decision makers.
Work with marketing on technical differentiation and generation of technical proofs for use by the customer team.
Develop, present, and respond to proposals for specific customer requirements.
Coordinate, develop and deliver product demonstrations which display the value of our solutions.
Works closely with customers to define new test cell opportunities and support existing sustainment activities. Travel requirements could be 25% or greater.
Lead in new product introduction with integration at customer sites with project management, hands-on integration, and training activities.
Support emerging markets, acting as a liaison between customers and the engineering, marketing, and operations teams to help with their product development.
Keep informed and present updates on competitors, industry news and trends, products services, relevant information about legacy, existing, emerging technologies, and the latest product-line development.

Required DDR Validation Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Define, develop, and execute post-silicon validation test plans on both pre-silicon emulation setups and physical silicon platforms in the lab.
Lead the bring-up of silicon, troubleshooting and identifying root causes of complex hardware and software issues.
Work closely with Architects, Design Engineers, Firmware/Software developers, and production teams to drive bug fixes and ensure feature functionality.
Provide comprehensive functional coverage for our custom designs, driving the transition from a prototype chip to a fully realized product deployed globally.

Required Emulation Hardware Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Maintain and upgrade emulation models and infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team and customers, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic design automation (EDA) tools, licensing, and job management in our infrastructure.
Support emulation team members with debugging hardware, tooling, and project-specific issues.
Help to bring up external interfaces (e.g., DDR, Peripheral Component Interconnect Express (PCIe), Ethernet, etc.) on the emulation platforms and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

Required Senior Silicon DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).