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We are looking for a Design Integration Engineer to join our GPU Network Team within the Chip Design Group. This is an exciting opportunity to be part of a growing and expanding team that is shaping the future of GPU networking silicon. Youll work in a dynamic, technology-driven environment where your contributions make a real difference,

with opportunities for growth, learning, and leadership.


Join one of the most desirable employers in the tech industry and help us build the next generation of GPU networking silicon.

What youll be doing:

Drive chip-level integration for advanced GPU networking silicon projects.

Collaborate with architecture, RTL design, verification, FV and physical design teams to ensure seamless integration and optimal performance.

Develop and maintain integration flows, methodologies, and automation to improve efficiency and quality.

Perform RTL synthesis, timing analysis, and support verification and post-silicon activities.

Handle Clock Domain Crossing (CDC) checks and ensure robust design practices.

Work closely with multiple teams across architecture, micro-architecture, backend, and firmware to deliver high-quality silicon.

Contribute to state-of-the-art technologies delivering industry-leading throughput and ultra-low latency for GPU networking solutions.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:
You will be in charge of state of the art Design for Test/ATPG flows and implementation.
Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.
Inventing and maintaining automation flows that provide the short test time to production.

We are seeking an exceptional Senior Director to lead our Networking Solutions Validation Group. Networking is a critical component of every AI factory and cloud deployment. As part of the Networking Cluster Solutions (NCS) group, you will play a key role in ensuring that our networking solutions perform at scale and deliver SOL-level performance. This role offers a unique opportunity to gain deep insights into our cutting-edge products and technologies. Your primary responsibility will be to lead a verification team tasked with validating all networking software and hardware solutions at scale, ensuring optimal performance.

What Youll Be Doing:
Build and lead the Networking Solutions Validation group, including hiring top talent and developing future leaders.
Collaborate closely with the NCS performance team, cross-functional engineering, architecture, and product teams to define and execute test plans on NCS clusters.
Partner with internal NCS teams to establish and implement validation methodologies and processes.
Envision and develop automation systems to optimize SOL execution
Drive innovation and showcase our Networking Solutions from the customers perspective

We are looking for a Firmware Engineer to join the NIC Firmware team at the Yokneam site. The Firmware team develops cutting edge networking features for cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced.

What you will be doing:

Work closely with the architecture and different software design teams.

Implement new features in the core of our NIC firmware in pre and post silicon environment.

Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.

Gain a deep understanding of system debug, networking technology and stacks, as well as the HW/FW/SW relationship.

You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed.

We are looking for a DFT Verification Engineer for developing the next generation DFT technologies.

As a DFT Verification Engineer, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.

As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.

Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

We're looking for a passionate Junior Firmware Engineer to join our PCIe Firmware team.

You will be part of a team whose mission is to develop cutting-edge technology for our network adapters, building the core of the next generation of our devices. In a company at the epicenter of the AI revolution, you will use the most advanced tools to build the foundational hardware that powers it. This is a chance to have a direct impact on our technology by solving sophisticated technical challenges and ensuring our customers can build the future of super-computing and AI fabrics.

What You'll Be Doing:
Design & Develop: Play a key role in the design, development, testing, and optimization of firmware for next-generation network adapters.
Collaborate Across Teams: Partner with world-class chip design, verification, software, and architecture engineers to define and craft new low-level firmware flows.
Solve Complex Problems: Investigate, debug, and resolve challenging firmware issues, contributing to robust, long-term solutions.
Drive Innovation: Help improve our team's methodologies and automated processes, contributing to our knowledge base and making everyone more effective.

We are searching for a highly motivated, excellent Software Engineer for design and verification to join the software tools group. You will design and develop tools that enable developers worldwide to harness the full power of our products. The successful candidate will show a strong background in C++ programming, strong documentation, and writing skills, take ownership of parts of the codebase, good communication and ability to integrate well as part of the team and organization, and motivated to solve sophisticated problems, developing tools for management, configuration and debug of all our networking products.

What you'll be doing:

As a valued member of the team, you will be involved in the technical design and implementation of numerous features working in an Agile environment. You will write code in C, C++ and Python, in OOP methodology.

Develop tools for management, configuration and debug of our networking products.

Effectively estimate and prioritize tasks in order to create a realistic delivery schedule.

Write fast, effective, maintainable, reliable and well documented code.

Collaborate with multiple development teams on new features.

Provide peer reviews to other engineers.

Document designs, and review documents with stake holders.

Demonstrate growth in technical and non-technical abilities.

Prepare and develop test plans for new features.

We are looking for best-in-class Chip Design Verification and Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating new chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you'll be doing:

Take a crucial part in developing our next-generation chip controller.

Design and verification with challenging multi-discipline context.

Take part in the development of all our networking and GPU networking chips and systems.

We are looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.

Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.

Power estimation and power modeling.