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Build the future of AI in the world of Cloud Infrastructure. You'll design innovative solutions powered by AI and help shape where we're headed as a company.

Why This Role Rocks:

Develop cutting-edge AI solutions - We're harnessing LLMs to solve real cloud infra problems, not just for buzzword points
We build the future - AI SRE became the hottest market in the cloud infra space - its our job to lead it.
Your ideas become reality - Propose solutions, lead initiatives, and see your impact
Shape our tech direction - You'll have a real voice in our technical strategy.
FULL Ownership: We believe in taking developments end to end. From ideation all the way to production.

As a Senior Backend Developer , youll be responsible for designing, developing, and maintaining our product across all teams. Whether its optimizing cost insights, building advanced troubleshooting capabilities, or developing Kubernetes-native agents and operators, youll work end-to-end on critical features - from design to production - in a fast-paced, CI/CD environment.



What youll do

Design, develop, and maintain core components of the product
Work across the stack to deliver new features from start-to-end
Deploy new features to production and ensure they run smoothly at scale
Improve performance and overcome scalability limits in high-volume environments
Collaborate with your team to plan and prioritize the most impactful projects
Write clean, maintainable, and scalable code in Golang (and occasionally other languages)
Ensure high code quality through automated testing and code reviews
Stay ahead of emerging software engineering trends and bring fresh ideas to the table

we are looking for a Engineering Team Lead.
In this role, you will take an integral part in the creation of a new and innovative SaaS product.
If you are a talented software engineer that likes to solve complex problems and looking for your next challenge we want you to join our team!
What youll do: As the Team Leader , you will lead a talented team to design, implement, and deploy scalable data solutions for an innovative SaaS product. Youll be responsible for shaping the direction of a system that impacts millions of users worldwide. If you're an experienced manager with a strong technical background, ready to lead in a dynamic, fast-paced production environment, we want you on our team!
Responsibilities:
Collaborate effectively with cross-functional teams (Data Science, Security, etc.) to ensure alignment on business needs and security standards.
Manage the technical backlog, make critical decisions on product milestones, and ensure timely, secure, high-quality delivery and deployment.
Foster the growth of team members through mentorship, personal development opportunities, and the promotion of continuous improvement.
Identify, manage, and mitigate security risks across the data platform, maintaining high standards in all initiatives.
Define and implement methodologies to guarantee the performance, scalability, and quality of our data infrastructure.

We're looking for a technical Product Manager to join AI product team and own the roadmap for Klaudia - our autonomous AI SRE agent. You'll work directly with customers, solution architects and R&D leads to define how Klaudia senses, investigates, decides, acts, and validates across availability issues and reliability risks. It's a role for someone who can translate complex AI/infra tradeoffs into a sharp product strategy.

What you will do

Work on the product roadmap execution, aligned with mission and customer needs
Collaborate with engineering and design teams to drive AI to success
Conduct thorough market research, close work with sales teams and customer calls to identify trends, customer pain points, and opportunities for AI integrations
Effectively communicate product vision, progress, and outcomes to internal stakeholders and customers
Define KPIs around AI capabilities and utilize data-driven insights to make decisions and product iterations

As a Wireless Firmware Architect you will focus on defining technical direction, conducting research and analysis, and providing architectural guidance for our Bluetooth embedded solutions.

The position emphasizes wireless protocol design and simulations, software architecture definition, technical planning, proof-of-concept development and performance optimizations.

Responsibilities:
Define comprehensive software architecture for our Bluetooth embedded solutions.
Establish firmware architectural guidelines and principles.
Support development teams with architectural guidance and consultation.
Integrate performance and power analysis requirements into architectural frameworks.
Create technical demonstrations to support architectural decision-making.
Monitor and analyze hardware implementations to ensure alignment with software architectural requirements.
Evaluate hardware design decisions and their impact on firmware architecture.
Collaborate with hardware teams to provide architectural input and recommendations.
Design and develop proof of concept (PoC) projects to validate architectural approaches.
Research and prototype emerging wireless technologies and methodologies.
Evaluate feasibility of new technologies and integration approaches.
Design and develop wireless protocol simulation frameworks, develop intelligent simulation environments for protocol validation and optimization.
Analyze new standards and specifications for architectural implications.
Track industry trends and emerging wireless technologies.

we are looking for a Senior Devops Engineer.
As a Devops engineer you will be a part of a team that serves one of our products and play a critical role in designing, building and maintaining our whole devops stack - from code to production and ensuring that we will have a state of the art system.
What youll do:
Be a part of a team of 3 devops engineers
Work closely with our R&D groups and teams including developers, data teams and architects
Work both on infrastructure and on CI/CD areas
Work on our devops stack such as Grafana, ArgoCD , P8s , Git, etc

We are looking for a hands-on GTM AI Engineer to design, build, and deploy AI-powered workflows and automations across our go-to-market (GTM) systems.
This role sits at the intersection of business operations and technology, and acts as the engine behind revenue intelligence, process automation, and scalable pipeline generation systems.
You will be a technical force multiplier for our GTM team including creating workflows, agents, and integrations, embedded directly into core business systems (e.g., CRM, marketing automation, support tools).
This is not a traditional software engineering role, but it requires strong technical execution and ownership across the full lifecycle.
What youll do:
Design, build, and maintain production-grade AI workflows and automations to streamline GTM execution (e.g., lead enrichment, routing, research, follow-ups, CRM hygiene, and customer handoffs)
Develop and deploy LLM-based solutions, including prompt-driven workflows, reusable prompt libraries, and AI agents embedded within business systems
Build and maintain integrations and data pipelines across CRM, marketing automation, enrichment tools, and internal systems to ensure reliable, connected data across the funnel
Own workflow performance, review success metrics, iterate and demonstrate business impact.
Build and maintain AI-assisted pipeline inspection tools to give RevOps and Sales Leadership real-time visibility into deal health
Identify opportunities to reduce manual work and improve efficiency across RevOps, Sales, Marketing, and Customer-facing teams
Partner with cross-functional stakeholders to map processes, identify bottlenecks, and prioritize high-impact automation opportunities
Drive adoption through enablement: documentation, training, and ongoing feedback loops
Evaluate and implement new tools and technologies based on ROI, scalability, and maintainability

We are seeking PHY Algorithm Technical Leader, Silicon One Israel
Meet the Team
You will join the SerDes System Algorithm team within Silicon One High Speed in Israel, part of our silicon development organization. The team works across modem technology, system modeling, and signal processing for high-speed SerDes devices.
Silicon One is at the center of our ASIC group, building next-generation network devices for AI networks, the 5G era, and the future of routing. Our design center brings silicon hardware and software disciplines together in one site, combining a small-team startup atmosphere with the scale and stability.
Your Impact
As a PHY Algorithm Technical Leader, you will provide technical leadership for the development, modeling, configuration, and optimization of algorithms for advanced SerDes modem systems. You will work with the latest silicon technologies and processes to help build large-scale, complex devices at the edge of feasibility.
Your work will contribute to Silicon One, a unified and programmable silicon architecture designed for service provider and web-scale markets. The role requires technical depth in digital signal processing, modem behavior, and using MATLAB for algorithm development, with the ability to guide algorithm work from initial concept through advanced SerDes system implementation.
Provide technical leadership for research, design, and development of PHY and modem algorithms for high-speed SerDes devices.
Define and use system models to analyze modem behavior, signal-processing performance, architecture constraints, and algorithm tradeoffs.
Guide modem configuration, tuning, and optimization to improve performance, robustness, and implementation feasibility.
Use MATLAB for algorithm development, simulation, testing, and data analysis.
Guide technical decisions, review algorithm tradeoffs, and mentor engineers on complex PHY and modem development tasks.
Lead cross-functional technical collaboration with system, silicon hardware, and software teams to move algorithms from modeling into practical implementation.
Support lab-based validation and debug activities when required.

We are seeking a Physical Design Technical Leader.
Meet the Team
Physical Design team within Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Your Impact
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Required PHY Firmware Technical Leader
Meet the Team
Join the Silicon One PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.
We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.
Your Impact:
Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies
Who Youll Work With:
The Silicon One group, the center of our ASIC design efforts
Cross-functional teams including silicon design, firmware, and system
Global teams working together to deliver game-changing networking devices

Required ASIC Design Engineer - Silicon One
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Silicon One is seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices-Silicon One. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

We are seeking an experienced and highly motivated C++ Software Engineer to join the Compiler team of our Network Technology R&D organization, contributing directly to the evolution of next-generation networking products.
Meet the Team:
Our team builds firmware, SDKs, simulators, and compilers for the Silicon One architecture - the industrys first routing and switching silicon architecture unifying networking across all layers. You will work on pioneering technology that powers the future of the Internet.
You will be part of a global team working on the newest generation, which will be integrated across the entire portfolio of our devices.
You will collaborate with worldwide distributed R&D centers, gaining exposure to some of the most talented engineers in the networking industry. We look for people who love technology and engineering-people who thrive on innovation, continuous learning, and challenging whats possible.
Your Impact
Design, implement, and test a state-of-the-art optimizing compiler for Silicon One
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities
Solve complex resource management challenges across hardware pipelines
Design and implement new P4 language features that empower network application developers
Build and maintain the compiler toolchain for custom networking applications
Contribute to libraries, analysis tools, and supporting infrastructure
Collaborate with cross-functional hardware and software teams
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out.

We are seeking PHY Algorithm Engineer, Silicon One Israel
Meet the Team:
You will join the SerDes System Algorithm team within Silicon One in Israel, part of our silicon development organization. The team works across modem technology, system modeling, and signal processing for high-speed SerDes devices.
We are at the center of our ASIC group, building next-generation network devices for AI networks, the 5G era, and the future of routing. Our design center brings silicon hardware and software disciplines together in one site, combining a small-team startup atmosphere with the scale and stability.
Your Impact:
As a PHY Algorithm Engineer, you will develop, model, configure, and optimize algorithms for advanced SerDes modem systems. You will work with the latest silicon technologies and processes to help build large-scale, complex devices at the edge of feasibility.
Your work will contribute to Silicon One, a unified and programmable silicon architecture designed for service provider and web-scale markets. The role requires technical depth in digital signal processing, modem behavior, using MATLAB for algorithm development from the idea to advanced SerDes systems.
Research, design and develop PHY and modem algorithms for high-speed SerDes devices.
Build and use system models to analyze modem behavior, signal-processing performance, and algorithm tradeoffs.
Configure, tune, and optimize modem behavior to improve performance, robustness, and implementation feasibility.
Use MATLAB for algorithm development, simulation, testing, and data analysis.
Collaborate with silicon hardware and software teams to move algorithms from modeling into practical implementation.
Support lab-based validation and debug activities when required.

Required Logic Design Engineer
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.