לוח משרות דרושים הייטק תוכנה בדרום, לחיפוש זה נמצאו 85 משרות

Were building foundational infrastructure to secure AI agents - including their identities, access patterns, and interactions with sensitive systems and data. This includes designing intelligent, dynamic mechanisms for ephemeral access control, secrets management, and agent/user identity tailored to the modern agent ecosystem.
Youll help define how agents (both machine and human-facing) authenticate, obtain scoped access, perform actions securely, and leave a verifiable audit trail.
This is a unique opportunity to be part of a start-up inside the company - building the platform from scratch at one of the most cutting-edge intersections of AI, identity, and security.
Responsibilities:
Own the design and development of secure, scalable services that enable AI agents to manage their identities, secrets, and access - directly protecting critical systems and data.
Take charge of agent authentication flows and real-time access policies, ensuring seamless, reliable just-in-time, least-privilege access.
Lead the evolution of MCPs and agentic AI, transforming innovative ideas into systems that define how intelligent agents operate at scale.
Collaborate with architects and engineers to shape and deliver high-performance platform components you can take pride in.
Write clean, maintainable, and scalable code that powers some of the worlds largest and most security-conscious companies.
Drive cross-functional efforts with platform, AI, and security teams to gather requirements, influence design decisions, and bring impactful solutions to life.

As a QA Engineer , you will play a key role in validating and improving our products, ensuring high quality.
You will join RADs family, as part of our team in Beer-Sheva, collaborating closely with software development teams in an agile and dynamic environment.

Location: Beer Sheva. Hybrid option once a week.

Responsibilities
Design and execute test plans and test cases based on system requirements
Identify, investigate, and report software bugs, while tracking them through resolution
Create and maintain clear test ation and reports
Collaborate with R&D teams to provide QA input throughout the development lifecycle
Communicate risks and quality concerns that may impact future releases

We are building the software foundation for the next generation of AI infrastructure. As AI workloads continue to evolve, Kubernetes and the cloud-native ecosystem must evolve with them.

Our teams mission is to make Kubernetes the best platform for AI workloads. We work upstream with the Kubernetes and CNCF communities to design new APIs, build production-grade implementations, and shape the future of cloud-native infrastructure for AI.

As a Senior Software Engineer, you'll tackle the most challenging problems at the intersection of Kubernetes, distributed systems, and AI infrastructure.


What you'll be doing:

Design, implement, and upstream new capabilities for Kubernetes and CNCF projects.

Collaborate with engineering teams across us to identify AI infrastructure challenges and solve them through upstream innovation.

Work closely with Kubernetes SIGs, Working Groups, and the broader open-source community to design and implement new capabilities.

Participate in architecture discussions, API design, technical proposals, and code reviews.

Build reliable, scalable infrastructure software for next-generation AI workloads.

Write clear technical documentation and design proposals.

We are looking for best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join accelerators IP group in Beer-Sheva, working on RiscV processor IPs.

Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work might involve any or all aspects of chip development: Verification, Design.

Work closely with Firmware and other groups around the globe.

We are seeking a Front-End Integration Engineer for the NIC Silicon group. Join our team in our Networking business unit and be part of the innovative build and implementation of the next generation Network Adapter Silicon chips. Contribute to the development of powerful communication devices.

What You'll Be Doing:

Own and maintain Continuous Integration pipelines. Monitor, complete, and fix daily and nightly CI flows in front-end build areas. These include Lint, Synthesis, Equivalence Checking and Simulation.

Automate EDA Flows: Build, develop, and maintain robust automation scripts using Python, Tcl scripting, and Shell to integrate EDA tools (Synopsys, Cadence) into automated build pipelines.

Manage Perforce Integration: Maintain multi-IP branch/stream strategies, manage workspace specs, complete hardware build drops, and handle release labels/tags in Perforce (Helix Core).

Support Engineering Teams: Act as the primary point of contact for RTL and verification engineers to debug flow crashes, bottlenecks, environment setups, and CI failure reports.

Enforce Quality Gates: Implement automated check-in and change list triggers to run sanity checks, linting, and style enforcement before code is committed to main streams.

Optimize Infrastructure: Monitor compute farm resources (LSF) and storage usage to reduce pipeline runtime and improve overall execution efficiency.

We are rapidly growing into new verticals, and we are seeking a visionary Developer Relations Senior Manager to broaden our impact. In this regional leadership role, you will champion Israels growing AI ecosystem, managing a high-performing team of Developer Relations Managers.

You will lead technical projects in GenAI/ML application development, consumer internet, and embedded AI systems. Working at the crossroad of engineering, strategy, and community, you will promote our hardware and SDK offerings. This role supports faster adoption of GPU-accelerated technologies by developers, startups, and ISVs. If you are a technically fierce, highly autonomous leader who thrives in a matrixed environment and wants to build the future of AI, let's talk.

What Youll Be Doing:

Lead & Mentor: Guide, collaborate and encourage a regional team of Developer Relations Managers covering Israel's dynamic AI ecosystem.

Drive Technical Strategy: Architect and complete a comprehensive developer adoption strategy for key industries, ensuring our platforms remain the gold standard.

Build Technical Alliances: Establish deep, positive relationships with CTOs, engineering leads, startups, and ISVs within the local ecosystem.

Evangelize & Accelerate: Act as the ultimate technical mentor and focal point for the developer community. Help developers unlock the full value of our SDKs and hardware to solve complex, real-world problems.

Champion the Community: Lead our presence at targeted developer events, hackathons, and industry activities.

Bridge the Matrix: Collaborate across internal product divisions, sales geographies, solution architects, and marketing teams to align our local ecosystem strategy with global value messaging.

The System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip - PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams.

What you'll be doing:

Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out.

Defining and implementing the SOC clock and reset architecture together with the micro-architecture team - collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design.

Owning clock domain crossing infrastructure and CDC closure across the SOC.

Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power.

Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness.

Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.

Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks.

Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable.

Supporting emulation, firmware, and post-silicon bring-up customers of your design.

We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.

Join us, the industry leader in high-speed communication devices, as a Physical Design Engineer in our Networking Silicon engineering team. You will develop innovative chips with outstanding efficiency and minimal latency. This opportunity lets you be part of a team leading modern technology, where your contributions will have a meaningful impact in a dynamic and inventive environment. We value collaboration, inclusion, and excellence, ensuring our technology remains world-class and our team members are supported to succeed.

What you'll be doing:

Engaging in the physical build of blocks according to specifications under challenging constraints, targeting efficient power, area, and performance.

Working on a variety of exciting builds, resolving complex timing and congestion issues with precision.

Engaging in all facets of physical chip build development (RTL2GDS), including synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Contributing to flow development to improve and innovate our processes.

Collaborating with a team of outstanding engineers to achieve flawless integration and implementation of builds.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.


What you'll be doing:

Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.

We are looking for a Staff QA Architect to join our elite team, contributing to the development of one of our strategic products for Cloud Security.
In your role, you will be responsible for developing and maintaining high-quality work procedures, leading the team to achieve better quality.
You will be involved in the full feature lifecycle - from gathering requirements with the product team to release - ensuring quality at every stage, including bug management and observability and defining QA work procedures, guidelines, and designing the entire testing process.
The ideal candidate will be responsible for leading quality activities across solution-level features, ensuring the highest standards of quality are met. This role requires a proactive individual with excellent leadership and communication skills, capable of driving quality initiatives and fostering a quality-focused mindset within the organization.
Comprehensive understanding of the product's functionality, target use cases, and the value it delivers to customers.
Lead the quality efforts across multiple interfaces with a proactive and assertive approach, serving as the key point of contact for all quality-related matters.
Define, implement, and manage QA processes, promoting a quality-driven culture and managing the quality backlog.
Define the overall testing strategy and tooling stack across integration, regression, and load/performance testing.
Drive an automation-first approach - collaborating with developers to ensure code is testable and observable.
Lead root-cause analysis for escaped bugs and define improvement actions.
Own CI quality metrics and dashboards (e.g., build stability, test flakiness, regression coverage).
Influence decisions regarding test environments, mocks, test data, and production parity.
Collaborate with the centralized quality group to ensure E2E test coverage.
Quality Point of Contact: Serve as the primary point of contact for quality-related matters concerning the unit or the cross-group feature.

Were building foundational infrastructure to secure AI agents - including their identities, access patterns, and interactions with sensitive systems and data. This includes designing intelligent, dynamic mechanisms for ephemeral access control, secrets management, and agent/user identity tailored to the modern agent ecosystem.
Youll help define how agents (both machine and human-facing) authenticate, obtain scoped access, perform actions securely, and leave a verifiable audit trail.
This is a unique opportunity to be part of a start-up inside the company - building the platform from scratch at one of the most cutting-edge intersections of AI, identity, and security.
Responsibilities:
Own the design and development of secure, scalable services that enable AI agents to manage their identities, secrets, and access - directly protecting critical systems and data.
Take charge of agent authentication flows and real-time access policies, ensuring seamless, reliable just-in-time, least-privilege access.
Lead the evolution of MCPs and agentic AI, transforming innovative ideas into systems that define how intelligent agents operate at scale.
Collaborate with architects and engineers to shape and deliver high-performance platform components you can take pride in.
Write clean, maintainable, and scalable code that powers some of the worlds largest and most security-conscious companies.
Drive cross-functional efforts with platform, AI, and security teams to gather requirements, influence design decisions, and bring impactful solutions to life.

We are looking for one architect to own both layers. Your foundation is deep platform and DevOps architecture: reliability, scalability, security, and cost efficiency of the cloud platform every R&D team builds on. Your growth edge is the AI layer: designing how agents are orchestrated, how they access tools and data safely, how we evaluate whether they work, and how we govern their cost and behavior in production.

We know agentic AI is a young discipline. We are not looking for a decade of AI experience that does not exist. We are looking for a proven platform architect who has spent the last one to two years genuinely building LLM-based and agentic systems in production, and who wants to own where this field goes inside a company that takes it seriously.

What Youll Do:
Platform & DevOps
Cloud Architecture: Own the architecture of our cloud platform, including GKE fleet design, VPC networking, IAM/Workload Identity, and multi-environment strategies across GCP (and AWS where relevant).
IaC & GitOps: Lead Infrastructure-as-Code (Pulumi, Terraform) standards, ArgoCD deployment patterns, and secure CI/CD paved paths (GitHub Actions, GitLab CI) adopted by all R&D teams.
Reliability & Observability: Own reliability architecture, including Disaster Recovery (DR) strategy and drills, P1 incident reduction, MTTR improvement, and observability platform architecture (Datadog, Prometheus, Grafana, OpenTelemetry) including usage and cost optimization.
FinOps: Drive FinOps as an architectural discipline-rightsizing, idle-resource elimination, unallocated-spend attribution, and cost-aware design reviews using tools like Kubecost or GCP Cost Management.
Agentic AI

Agent Architecture: Design our agentic AI ecosystem, focusing on agent orchestration frameworks (e.g., LangChain, LangGraph, CrewAI, AutoGen), tool/MCP (Model Context Protocol) interfaces, vector databases/memory strategies (e.g., Pinecone, Qdrant, pgvector), and production AI deployment patterns.
Evaluation & Guardrails: Build the evaluation and guardrail layer for AI in production using frameworks like Ragas, TruLens, or LangSmith. Define permission models, human-in-the-loop checkpoints, audit logging, and policy-as-code for AI usage.
AI FinOps & Monitoring: Own AI cost observability, token spend monitoring, model routing strategies (optimizing for cost/quality/latency trade-offs), and real-time alerting on runaway model usage.
Reference Architectures & Standards: Define reference architectures for teams building AI features, RAG patterns, prompt versioning/management, and model API standards (OpenAI API, Anthropic, open-source models via vLLM/Ollama), driving high-leverage AI automation across R&D.

We are looking for a Senior Chip Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.

Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.

Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, FW and Post-Silicon validation.