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We are seeking a talented Program Manager to join our team. In this high-visibility, hands-on role, you will drive forward the development of our chip by managing the complete program lifecycle, from architecture to successful tapeout, ensuring deliverables meet scope, schedule, and quality requirements.

Responsibilities
Lead the planning, development and implementation process of cross-functional teams focused on product delivery.
Drive the execution of the hardware roadmap by managing the complete lifecycle from architecture definition to tapeout.
Partnering tightly with Architecture, RTL Design, and Design Verification (DV) leads to identify bottlenecks, track coverage metrics, and mitigate risks before they impact the tapeout schedule.
Define the core operational processes and modes of work for the entire HW group, building and refining the stage-gate reviews required to transition smoothly from architecture into implementation and verification.
Oversee project monitoring, reporting, and risk management, from initiation to delivery, addressing intergroup dependencies to ensure timely and successful completion.
Lead process and methodology improvements, proactively addressing issues to achieve business goals.

we are looking for a talented and experienced design manager to drive and help our group to get to the next era of computer architecture. In this position, you will design the critical parts of future chips. You will be involved in the full design cycle from architectural requirements into micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.



Responsibilities
Be accountable for your team's milestones & timelines
Leading your team members and developing their abilities
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators, monitor and report execution progress to enable prioritization and clear decision-making
Acquire the system Architecture and be part of the leading technical FE forum

we are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product

Responsibilities


Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip

Come help lead the design and development of one of the most ambitious products at the forefront of compute technology!

Responsibilities
Lead a physical design team responsible for all stages of the physical design process-floor planning, placement, clock tree synthesis, routing, timing, and power optimization at both block and subsystem levels.
Mentor and guide a team of physical design engineers through all stages of the design flow.
Collaborate closely with project managers and other technical leads to ensure timely delivery and successful completion of projects.
Drive the technical direction of the physical design process to ensure efficient, high-quality outcomes.
Develop and implement best practices for physical design and continuous improvements of design workflows.
Optimize designs for performance, power, and area (PPA) to meet project goals.
Ensure compliance with DRC (design rule checking) and LVS (layout versus schematic) requirements. .
Drive timing analysis and closure, working closely with the RTL design team to resolve timing violations.

We are looking for an experienced, talented CPU ASIC front-end design expert and technical lead. In this role, you will take part in developing cutting-edge high performance best in class RISC-V CPU, from definition stage through planning stage and the development of new features while solving challenging implementation problems and ending in successful tape-out and product bring-up .




Responsibilities
Learn high performance RISC-V Arch and algorithms
Define and drive the design of advanced and super complexed blocks from micro-architecture phase to tape out.
Work closely with various teams to drive execution (SW, Architecture, verification, BE, FPGA, postSi etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making

we are looking for a talented and experienced engineer to participate in designing the next era of computer architecture. In this position you will take part in designing the critical parts of future chips. You will transform architectural requirements to micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.

Responsibilities
Define and drive the design of advanced blocks from micro-architecture phase to netlist
Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts
Leading processes relating to power optimization
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making

we are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.

Responsibilities
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet timing, area, and power constraints
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip integration

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.





Responsibilities
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches
Work closely with the verification team to ensure the quality of the product
Build and maintain a smart and scalable verification environment that ties into various systems
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design

We are seeking a talented engineer to work on our AI software stack-specifically, the low-level optimization of AI models and kernels for our unique hardware architecture.

Responsibilities
Develop our optimized AI libraries and related components in the SW stack.
Drive the performance optimization of AI models running on our unique architecture.

Our team is looking for a skilled professional to join the AI software group. In this role, you will focus on our AI kernel compilers, ensuring our hardware delivers peak optimization for sophisticated and custom AI kernels. You will work extensively with various kernel infrastructures, including Triton and CUDA, while collaborating closely with our AI graph compiler teams.



Responsibilities
Develop our AI kernel compilers and related components in the SW stack.
Drive the performance optimization of AI models running on our unique architecture.

we are looking for talented networking software engineers to develop an innovative new communication stack. Were starting from the ground up, rethinking existing protocols and network accelerators while designing both hardware and software for a new low-latency compute platform. We care about results and insist on doing things right. Our engineers are not siloed into narrow areas; our ideas are cross-fertilized among teams. Our technical backgrounds are diverse and we don't have preconceived approaches or cookbooks, so come and invent! The hardware teams are just a few steps away and really like hearing our ideas. This is a unique opportunity to develop creative solutions from concept to implementation.

Responsibilities
Take part in developing a networking stack from the ground up:

Analyze customer applications and explore creative ways to accelerate them in hardware or software
Find the best ways to process packets on hardware platform
Participate in architecture of future NIC generations
Develop user-space libraries and benchmarks for low-latency communication
Work closely with the hardware teams to offload key features into the next generation of products

We are seeking a talented Code Generation and Optimization Expert to join our bleeding-edge CodeGen team in Israel. In this high-visibility, hands-on role, you will play a pivotal part in building next-generation runtime compiler.

Responsibilities
Design and maintain the distributed and heterogeneous executable that is generated by our compiler stack.
Using the MLIR framework, transform high level compiler outputs into hardware-specific binary images, memory mappings, execution parameters, resource allocation, region grouping, and cross-domain coordination for distributed systems.
Design and maintain the API layer (libRT.a) connecting compiler-generated code with runtime services, ensuring seamless integration across different execution domains.
Collaborate closely with hardware, architecture, verification and other compiler teams to align software with hardware requirements and behavior.

We are looking for a passionate Senior Software Engineer to join our Simulation development team. Our team is growing, and we are looking for hardworking and experienced engineers to take part in building advanced networking simulation solutions. You will be part of a team developing next generation NIC and Switch simulation, works closely with other SW R&D teams and SW Architects.

What you will be doing:

Design and develop advanced features simulating our world class Switches.

Develop solutions using advanced virtualization technology.

Write clean, efficient and maintainable code.

Collaborate with team members, SW R&D, Architects, Chip Design and FW.

We are seeking an exceptional Network Engineer to join the Vertical Verification Group. As a senior engineer, you will contribute to the Vertical Verification work, concentrating on validating and improving complex Ethernet and InfiniBand systems within our Data Center and HPC environments.

You will play a key role in testing advanced networking features, building complex customer-like topologies, and ensuring our products meet industry-leading benchmarks of performance, efficiency, and quality. You will collaborate closely with architects, software engineers, and hardware teams across NIC, HCA, switches, CPUs, and GPUs in a fast-paced and highly technical environment. This is an outstanding opportunity to join a highly skilled team and contribute significantly to groundbreaking technology!

What youll be doing:
Review architecture, build, and requirements for new networking features across Ethernet and InfiniBand portfolios.
Compose and build complex testbed topologies that emulate customer environments.
Implement, run and optimize integration test plans including functional, regression, and performance testing.
Identify, reproduce, and debug issues; work closely with R&D to drive root cause analysis and resolution.
Collaborate with automation teams.
Analyze and optimize network performance, latency, and efficiency.
Provide clear status updates, reports, and insights on system quality and performance.