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we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You wont just be using tools; youll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.


Key Responsibilities

Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes
Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows
Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics
Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows

we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world's largest AI clusters.

As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities


Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor technical reviews

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.


Key Responsibilities


Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
Own the design database structure and version control to ensure team alignment and data integrity
Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.

Key Responsibilities

Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs
Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners
Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy
Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids
Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs
Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA
Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

we're seeking a visionary Staff Physical STA Expert to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the sign-off methodology for chips that power the world's most advanced AI clusters.

As a Staff Physical STA Expert , you will hold the keys to silicon success. You will be leading the STA activities end-to-end from Chip partition, Time budgeting through signoff of all the chips we develop. You will build and lead the STA team to run several chips signoffs in parallel. In addition, You will define the sign-off methodology for chips that power the worlds most advanced AI clusters. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

Take full ownership of the STA flow and sign-off methodologies. You will establish the rigorous criteria that ensure our products succeed in the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams. You will lead timing reviews and work closely with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints from the ground up, ensuring they are robust across multi-scenario environments
Tackle the challenges of cross-chip clock distribution networks and sophisticated margining techniques, ensuring robust silicon across all process corners
Have a passion for better workflows? Youll participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and in-house automation to make our sign-off process faster and smarter

Are you looking for a great opportunity to further your career? we are investing in the rapid growth area of Hardware Assisted Verification (HAV).
Our most successful multi-national customers are using our company HAV platforms to verify some of the worlds most advanced System on Chip (SoC) designs. HAV solutions are expanding to a wider audience of smaller companies who are benefiting from early software development and ultra-fast hardware verification through hosted services.
we are looking to hire a Senior Consultant with either Emulation or FPGA prototyping knowledge and experience. This role is ideally suited to someone with a good understanding of HAV platforms who can guide customers through successful HAV deployment and design validation. This is a great opportunity to work with some of the most interesting and innovative people and companies across the semiconductor industry.
The consultant role will be mainly focused on technical services delivery. This could range from platform enablement to methodology guidance. Interactions may be direct with the customer or collaborative through a wider technical team. This position will require a combination of remote, office and onsite working. As a consultant, you will also be expected to uncover opportunities, scope engagements, promote offerings, and grow new business.
Key Responsibilities
A good understanding of HAV platforms and infrastructure (e.g. Strato, Primo or proFPGA enterprise-level systems would be preferable)
A good understanding of HAV compilation and runtime flows (e.g. Veloce or VPS would be preferable)
Practical insights into the application and usage of HAV
Knowledge of design mapping, testbench mapping and pre-silicon validation
Familiarity with HAV debug solutions (probes, waveforms, assertions, coverage, etc.)
Knowledge of virtual TestBench eXpress (TBX) and/or In-Circuit Emulation (ICE) use-cases
Proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification
Strong background in functional verification, RTL synthesis, design partitioning and place-and-route
Conversant with SoC design and architecture concepts.

we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities

Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects

We are looking for an experienced system engineer to participate and lead the development of a radio-based drone detection and mitigation system as part of the company products.
Responsibilities:
Lead features and platforms from ideas to releases.
Guide and participate in the research and analysis of both proprietary and standard radio communication
protocols.
Develop and optimize algorithms for scanning, signal separation, antenna selection, etc.
Define requirements and guide other multi-disciplinary teams (SW, Modem algorithms, DSP, and FPGA) through
implementation and debugging.
Analyze and define complex system behaviors, state machines, algorithms, and event-response logic, including
radio link budget considerations.
Perform independent, hands-on debugging and optimization for system problem-solving using tools like
MATLAB, Python, Excel, and other log analysis software.
Gain a deep understanding of the full system to guide and support development, testing and validation teams.

Required Senior Verification Engineer (FPGA)
Our people are our greatest strength - and technology is our passion. Our team of innovators and subject matter experts, including veterans of elite military intelligence technology units, is transforming the way organizations protect themselves from drone threats.
As the global leader in cyber-takeover counter-drone technology, we design and deliver advanced, software-defined solutions that empower our customers to detect, take control, and safely land unauthorized drones - with precision and reliability.
Every day, we push the boundaries of innovation to meet real-world security challenges across industries and environments. Were proud of our cutting-edge technology, our global reach, and the impact we make in securing the skies.
Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment - those who want to be part of the next generation of airspace security innovation.
Join us and help make the world a safer place.
Work with the worlds leading cyber-takeover counter-drone technology provider and shape the future of safe airspace.
Lead the functional sign-off for complex FPGA designs by architecting scalable, reusable UVM-based verification environments.
You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.
Key Responsibilities:
Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.
Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.
CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).
Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.
Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.