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Required Senior SoC Power Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our Platforms Infrastructure Engineering team designs and builds the
hardware and software technologies that power all of our services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of users.
Responsibilities
Develop methodology of SoC roll up of power reduction, projection, configuration, test plan and tools.
Work intact with Architecture, Frontend and Backend teams driving power reduction features (both logic and circuit).
Work with power delivery and packaging teams on simulations and scenario definitions.
Work with Architecture and design verification (DV) to define power scenarios and tests, debug, and integrate into the flow. Track whether power goals are met throughout execution.
Lead the power of a project. Own project priorities, and allocation of technical resources within the project, informing and escalating appropriately when external factors impact execution.

We are looking for a Senior Product Engineer to join a global team of a Product Engineers that own a technical success and customer satisfaction across multiple high-impact projects. This role is deeply rooted in data analytics; youll be working at the intersection of silicon, systems, and software to deliver high-value insights to customers.

Responsibilities
Performing post-silicon and system-level data analysis and providing insights on data extracted from post-silicon stages.
Supporting customers with analytics platform problems solving and new features introduction.
Drive integration of proteanTecs analytics platform within customer environments, bridging silicon, test, and system-level domains.
Collaborate with R&D and data science teams to develop, validate, and improve advanced analytics algorithms.
Troubleshoot complex silicon/system issues through data-driven insights.
Partner with internal stakeholders (design, software, product) to influence roadmap and execution.
Act as a technical professional in customer onboarding, support, and ongoing engagement.

Join the Front-End Design team, at the core of silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
Your Impact:
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.
Your Impact:
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.
Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.
Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.
Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.
Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.
Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.
Help bridge between general DV methodologies and DFT-specific design and verification needs.

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the DFT team.
This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.

we are looking for a Physical Design Manager.
You'll be part of the Cisco Silicon One team, which is at the heart of Ciscos software and ASIC design efforts.
As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

we are looking for a ASIC Leader.
Your Impact:
Review micro-architecture specifications
Supervise verification team members and provide professional guidanc
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are looking for a motivated and detail-oriented Safety Laboratory Technician to join our Hardware Department lab team at our Tel- Aviv office.

The successful candidate will perform safety testing of company products in accordance with international safety standards. Comprehensive professional training will be provided as part of the role.

Key Responsibilities
Perform safety testing of company products in accordance with international safety standards.
Operate laboratory test and measurement equipment.
Set up, execute, and document safety test procedures.
Prepare clear and accurate test reports.
Maintain laboratory equipment and ensure compliance with laboratory procedures.
Work closely with engineering and regulatory teams to support product certification activities.

We are looking for a versatile Senior Software R&D Engineer and a dedicated team member to join our multidisciplinary group. This role places a heavy emphasis on hardware bring-up, low-level software development, and collaborative engineering. You will be a core player in a tight-knit team, moving seamlessly between different phases of system creation-from architecting board support packages (BSPs) and troubleshooting new hardware boards to designing high-performance application features.

Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.



Responsibilities:
Active Team Member: Collaborate daily within a diverse R&D team. Brainstorm solutions, conduct peer code reviews, and share knowledge to elevate the teams capabilities.
Hardware Bring-up & BSP: Lead the software-side bring-up of next-generation hardware. Design, develop, and debug Board Support Packages (BSPs) to seamlessly bridge the hardware-software boundary.
HW/SW Integration: Partner closely with hardware engineers to diagnose system-level bottlenecks, read schematics, and ensure optimal hardware performance.
Real-Time Feature Implementation: Design and develop high-performance software features and real-time application layers for our flagship product.
Product Implementation Design: Translate complex product requirements into scalable, highly reliable software designs and system architecture.