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Required DDR Validation Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Define, develop, and execute post-silicon validation test plans on both pre-silicon emulation setups and physical silicon platforms in the lab.
Lead the bring-up of silicon, troubleshooting and identifying root causes of complex hardware and software issues.
Work closely with Architects, Design Engineers, Firmware/Software developers, and production teams to drive bug fixes and ensure feature functionality.
Provide comprehensive functional coverage for our custom designs, driving the transition from a prototype chip to a fully realized product deployed globally.

Required Senior CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving force behind groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required SOC Quality and Reliability Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the-art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. You will have an opportunity to create silicon and follow it into the field and back to drive improvements for the next-generations of chips.
You will have an understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis is expected. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. You will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.
The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Establish and direct the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge and latch-up (ESD/LU), and biased highly accelerated stress test (b/HAST)) and conduct in-depth failure analysis to resolve quality issues.

Required Signal/Power Integrity Engineer, PhD Graduate
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Simulate high speed interface electrical behavior using HSPICE or other circuit simulators.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Collaborate extensively with cross-functional teams, including ASIC architects, digital/analog designers, physical design/layout engineers, and system engineers, to define specifications and resolve integration challenges.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR) , Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Establish robust design rules and guidelines for optimal signal/power integrity during PCB and package layout, ensuring high production yield and reliability.

Required Senior Verification Engineer, Digital Signal Processing, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you own the verification strategy for high-speed Physical Layer (PHY). You aren't just looking for RTL bugs, you are looking for system-level failures. You will lead the effort to verify how the digital DSP interacts with the analog front-end.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities:
Lead the verification strategy for high-speed PHYs (112G/224G), defining the test plan for top-level integration and mixed-signal boundaries.
Architect and implement mixed-signal verification flows using Real Number Modeling (RNM) or SystemVerilog-AMS to verify the interaction between Analog Front Ends (AFE) and digital DSP.
Design specialized testbenches to verify the stability, convergence time, and tracking capabilities of adaptive algorithms (e.g., LMS, Zero-Forcing) across Process, Voltage, Temperature (PVT) corners.
Develop tests that simulate real-world data center conditions, including link bring-up, auto-negotiation, and error-recovery protocols.
Act as the primary verification interface for the Signal integrity and Power Integrity (SI/PI) and Analog teams, ensuring that physical channel impairments (loss, crosstalk, reflections) are accurately reflected in the Design Verification (DV) environment.

we are looking for a Senior ML Engineer.
Responsibilities:
As a Senior Machine Learning engineer at Substrata, you will be working directly with our Head of R&D and will take a major role building our Pragmatic Intelligence Engine using and experimenting with S.O.T.A Deep Learning architectures, including: Multi-Layer Perceptron Neural Network, LSTM, mLSTM, CNN, RNN, VDCNN, etc.

We are looking for a Senior Algorithm Developer with experience in NLP and LLMs, who is highly motivated, collaborative, and results-driven individual who can work both independently and as part of a multidisciplinary team. The ideal candidate has a strong can-do attitude, excellent problem-solving skills, and a passion for leveraging AI to solve meaningful challenges in text analysis in the medical domain.

As part of the AI team you will:

Design, develop, implement, and evaluate robust, scalable AI algorithms and agentic workflows tailored to real-world challenges in clinical settings.

Prepare, process, and analyze complex medical data to support algorithm development and validation.

Ensure the reliability, performance, and accuracy of algorithms in production, including troubleshooting, testing, monitoring, and continuous improvement.

Collaborate closely with Product Managers and Clinical Specialists to translate clinical and business needs into data-driven solutions.

Research, develop and integrate cutting-edge text based alogirthms on medical text.

Apply NLP and Large Language Models (LLMs) to extract insights from medical texts and develop intelligent agents for optimized clinical decision support.

Stay up to date with cutting-edge advancements in GenAI, LLMs, and Deep Learning.

Organize and actively participate in seminars, book clubs, and conferences.

Main Technical Stack:

NLP/LLMs: Pydantic, Hugging Face Transformers, spaCy, Amazon Bedrock

Infrastructure: AWS, Docker

Programming Languages: Python

Deep Learning Frameworks: TensorFlow, Keras, Pytorch

We are looking for a Software Engineer to join our core Algorithm team as an dedicated data-core / platform engineer. You will support the algorithm engineers developing detection algorithms to design and build the infrastructure they run on: the object-detection (OD) pipeline, its orchestration and deployment, its data and model catalog, and the benchmark and labeling systems that drive model improvement. This is a high-autonomy role with real, end-to-end ownership of production systems from day one.

The technologies listed in this description are examples of our day-to-day - not a rigid checklist. We care far more about how you think, how you plan, how you debug, and how fast you learn than about which specific tools you have already used. If you love the craft of making things work and want to go deep, you can learn the rest here.

In the AI era, being a strong engineer means more than writing great code. It means operating as an architect who directs AI agents - designing the solution with clarity, then guiding them to execute it at a level and speed that wasn't possible before. We are building a culture where this is the norm, and we're looking for someone who is excited to work and grow in that direction.



What You'll Do

Take on hard, open-ended infrastructure challenges and make them work - designing, building, decoupling, and hardening the systems behind our object-detection pipeline, from data and model management to benchmarking, so everything runs reliably at scale.
Architect and build the backbone of the OD pipeline - orchestration (Airflow on Kubernetes), data plumbing (S3 / PostGIS / SQS), CI/CD, and deployment across multiple environments - designing clean interfaces and data contracts the algorithm team can build on with confidence.
Debug across the whole stack, wherever the problem leads - a stuck DAG, a flaky pipeline stage, a slow query, a GPU/driver mismatch - and turn one-off firefights into lasting fixes and better observability.
Own the data and model lifecycle: versioned datasets and model weights with clear provenance, and the labeling → export → retraining loop that keeps the models improving.
Learn fast and go deep. Pick up new tools and new layers of the stack as the work requires, and raise the team's engineering and operational standards as you go.
Partner closely with algorithm engineers and the data-collection / labeling operations team to turn research prototypes into robust, scalable production systems.
Integrate AI tools into your workflow and grow into operating as an architect who directs AI agents - designing the solution, then guiding them to build it.

We are looking for a Staff Algorithm Engineer to join our core Algorithm team - a high-autonomy group responsible for the algorithm and ML systems at the heart of 4M's mapping engine. This is a role for engineers who think in systems, bring cutting-edge computer vision and algorithmic thinking to ambitious real-world challenges, and own problems end-to-end with an entrepreneurial drive.

In the AI era, being a strong engineer means more than writing great code. It means operating as both an architect and a team lead - designing the solution with clarity, then guiding AI agents to execute it at a level and speed that wasn't possible before. We are building a culture where this is the norm, and we're looking for someone who is excited to work and grow in that direction.

You will work across computer vision and algorithm disciplines - researching solutions, designing experiments, and delivering production-grade implementations - while collaborating closely with data engineering and product teams.





What You'll Do



Research and implement novel computer vision and algorithmic solutions for challenging real-world problems - spanning perception, learning, optimization, and graph-based reasoning.
Own algorithm quality end-to-end: design experiments, evaluate results, and drive iterations until production reliability targets are met.
Work across disciplines - sharing models, methods, and insights with algorithm, data engineering, and product teams.
Monitor production model health proactively; identify degradation early and lead remediation efforts.
Integrate AI tools into your workflow and grow into the role of architect and team lead - designing the solution, then directing agents to build it.
Raise the bar on the team's technical culture through code reviews, knowledge-sharing, and rigorous algorithmic thinking.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Junior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.
As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.
Key Responsibilities
Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects.

We're currently seeking a Data Researcher to join our Data Team and help proactively guide our business growth through the provision of strategic perspective, market insight, and experience with analytical tools and techniques. You will work closely with product managers, medical analysts, and the engineering team and bring your expert analytical ability to provide key insights, recognize key opportunities, and drive strategic initiatives forward.

Responsibilities
Build and maintain data pipelines and dashboards to improve data visibility and reporting in production environments
Implement AI-powered workflows for internal and external uses
Work with product, medical, and engineering teams to turn data into insights and recommendations.
Conduct exploratory analysis to identify opportunities for new features, model their impact, and drive performance improvements.
Analyze product performance, user behavior, and interactions to showcase product value.
Define, measure, and build monitoring tools for key KPIs.
Visualize insights clearly to improve understanding and decision-making.
Support roadmap planning by identifying trends, gaps, and opportunities.