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looking for an hpc and ai data center engineer to join the networking cloud solutions hpc/ai infrastructure team. we are focused on building supercomputers and hpc clusters based on groundbreaking technologies. we are looking for a lab manager, be a key player to the most exciting computing hardware and software to contribute to the latest breakthroughs in artificial intelligence and gpu computing. take part of building large-scale compute and deep learning software and hardware platforms, work together and support many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions.
what you will be doing:
plan and build complex cluster and supercomputers in various of data center and labs
rack stack and cable management to ensure efficient use of space and easy maintenance
ensure data centers and labs power and cooling efficiency while optimizing rack space utilization
data centers and labs daily operation and support
installations for variety of infrastructure and solutions - cloud, vms, Storage, network, hpc and ai
perform troubleshooting - network, optic cabling, bare metal, operating system.
support research & development activities

our company is hiring a senior, hands-on engineer to lead technical innovation in our design verification (dv) automation infrastructure. this role requires a strong design/verification background combined with a proactive approach - identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. you will directly influence how verification is performed across our next-generation networking chips, enabling more scalable, efficient, and robust flows for complex asics powering the ai revolution. 
what you'll be doing:
lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
identify key challenges and inefficiencies in current dv methodologies and proactively propose and implement improvements.
work closely with dv engineers, design teams, and tool developers to ensure solutions are practical and impactful.
balance innovation with hands-on engagement in daily dv issues - keeping a strong connection to real-world challenges and support needs.
act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for dv automation.

come be part of our company, the industry leader in ai data centers. we are now innovating the future of data center, and defining the next generation of networking solutions. our team is dedicated to pushing boundaries and overcome the challenges involved in providing high performance data centers. as a network rdma algorithms architect, you'll contribute to our creative and cooperative setting, focusing on the connectx network adapter, spc-x end to end solution and more exciting technologies.
what you'll be doing:
conduct research and analysis on networking solution and end to end algorithms.
work with a creative and experienced team to outline the next generation of our rdma load balance and congestion control algorithms.
work on simulation environment and on real hw systems
engage with other research teams to develop proof of concepts using our technology.

we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

Our Formal Verification (FV) team is seeking a visionary AI Verification Engineer to join our elite Networking Chip Design group. Our team is unique: we define the infrastructure and drive the methodologies for proving the correctness of the worlds most advanced AI and networking architectures. We operate at the cutting edge, leveraging a sophisticated ecosystem of proprietary in-house formal tools and industry-leading vendor EDA solutions.

In this role, you will be a key architect in our "AI-for-FV" evolution. You will work in close collaboration with our internal CAD and Design Technology AI teams to enhance our in-house toolset with artificial intelligence. You won't just be using tools; you will be building the "brains" that sit on top of them-utilizing LLMs and Machine Learning to automate intent-to-proof workflows and debug complex chips with unprecedented speed.

What Youll Be Doing:

In-House Tool Evolution: Partner closely with internal CAD teams to integrate AI capabilities directly into our proprietary FV infrastructure.

Methodology Architecture: Define and evolve the FV teams specialized methodologies, moving from manual property writing to AI-automated assertions.

Next-Gen Orchestration: Develop and integrate AI agents and ML models that interface with our toolchain to automate "intent-to-assertion" workflows and optimize coverage and convergence.

Intelligent Debugging: Create AI-based debug assistants that analyze formal counter-examples, categorize failures, and autonomously suggest fixes for complex logic problems.

Collaborative Intelligence: Act as the bridge between the FV team, Design Technology AI, and CAD groups to ensure our AI solutions provide end-to-end efficiency from RTL to A0 tapeout.

Leadership & Training: Act as the authority on AI integration, training the broader team on how to leverage "human-in-the-loop" AI tools and automated methodologies.

We are seek a forward-thinking, innovative, and experienced Solutions Architect with hands-on experience.

By joining the team, youll take a part in the design and implementation of complex data center solutions, including solution architecture, HW and SW deployment, performance, and return on investment analysis. You will work with software developers and architects to research and analyze new, groundbreaking technologies.

The candidate is expected to have hands-on experience with data center technologies, including operating systems, virtualization and containerization technologies, storage, networking, and infrastructure as code (IaC) tools such as Ansible. A candidate for this position must excel at working independently as well as in a group, in a multidisciplinary, dynamic environment.

What youll be doing:
Implement cutting-edge, end-to-end data center solutions with modern applications.
Architect, develop, deploy, automate, analyze, formalize findings, and release summary reports.
Develop and release reference deployment guides and how-to tutorials.
Support company business units on complex solutions delivery by consulting, providing solutions designs, running POCs, etc.
Research technology trends and deliver best practices for integrating NVIDIA products and technologies.

We are seeking a Principal verification engineer to be a technical lead in the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and adopting new technologies. One of our main goals is to define, build and use best in class technologies make sure that the chip design team works in an efficient manner and provides high-quality deliveries at scale. This position offers the opportunity to drive foundational flows and have a profound impact in a dynamic, technology-focused company.

What you'll be doing:

Define groundbreaking methodologies to create a flawless experience for verification engineers.

Mentor and guide designers and verification specialists to tackle complex technical challenges.

Identify design risks, define the verification scope, and lead infrastructure development to ensure design correctness.

Technically guide the development process of shared verification code and infrastructure to be widely used by the global chip design team.

Partner with the design automation team to provide end-to-end solutions that unify verification, simulation, and automation.

Collaborate with EDA vendors to learn about innovative tools/technology and integrate them into our long-term verification strategy.

Lead verification strategies, training sessions.

Our New Product Introduction (NPI) team is growing, and We are now looking for a Chip Engineering Operations Program Manager! The Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the silicon schedule from bring-up to production release. We are looking for individuals who thrive in a dynamic environment, and are not afraid to roll-up his their sleeves and get their hands dirty. We desire a self-starter, with great communication skills; as well as a leader, with a deep sense of commitment. You will be responsible for developing wafer forecasts, schedule generation and management, supporting cross-functional teams, and mitigating any programmatic risks. You will also review and improve processes, and handle prototype demand.

What you'll be doing:

You own silicon bring-up schedule from power on to production release.

Negotiate silicon and board demand with teams and drive a bottom-up forecast.

Oversee and manage chip and board allocations across the company.

Lead prototype chip delivery to internal customers.

Track and coordinate engineering deliverables, key milestones and qualification/validation tasks in the new product introduction phase.

Identify and mitigate risks to schedules and programs.

Communicate status to cross-functional teams as well as upper management.

Continuously evaluate internal tools and processes and drive fixes to improve productivity.

Create new and fix existing processes between different teams.

Drive implementation of SW tools for data analytics and process evaluation.

We are looking for a Formal Verification Engineer for our Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:

In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.

You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of NVIDIA's core technology.

Learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.

Join our DOCA Verification team as a Senior Software Verification Engineer and help shape the future of Data Processing Unit (DPU) and network interface cards software. We are seeking a highly motivated and skilled engineer with hands-on technical experience to verify the design and implementation of next-generation software features, with a focus on solving modern hyper scaler advanced networking aspect like congestion control and optimized network usage.

What you'll be doing:

Collaborate with software, architecture, product, and DevOps teams to define test requirements, coordinate releases, and deliver high-quality products.

Take end-to-end ownership of features: develop test plans, implement, and fully automate testing (primarily in Python).

Design, build, and maintain automated test scripts and frameworks.

Validate software functionality and performance through system-level and integration testing in Linux-based and virtualized environments.

Analyze test results, file bugs, track issues to closure, and ensure robust solutions.

Drive continuous improvement in verification flows and contribute to process and methodology enhancements.

Set up, maintain, and optimize test environments using Linux, Docker, and virtual machines.

Monitor nightly regression systems, analyze failures, and provide thorough root-cause analysis across hardware, OS, and software layers.