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נאספה מאתר אינטרנט
16/04/2024
חברה חסויה
Location: Yokne`am and Tel Aviv-Yafo
Job Type: Full Time
With the slowdown in Moore's law, silicon power management and hardware power optimizations become a critical part of the development of silicon ASICs. We are positioning you for a key role to take on this challenge and become part of our team, so we can continue developing the best devices in the industry!

Our network horizontal power group is seeking for a highly-skilled, physical design engineer to explore, define and assimilate methods for optimizing our products' power with respect to performance and cost. In your role you'll be responsible to develop methodologies, improve tools and flows, driving power optimization and examine silicon power & performance. We are searching for a hard-working, highly motivated, engineer which has both excellent technical skills as well as outstanding personal skills.

What you will be doing:

Establish estimation and optimization techniques for RTL design and physical design teams.

Improve estimation quality and pre2post correlation.

Develop methodologies and flows across the organization for both pre and post-silicon analysis.

Improve RTL to gate level power aware flows and automation.

lead power execution teams with working methods and power model for various product lines.
Requirements:
What we need to see:

B.Sc. degree or equivalent experience in Electrical Engineering.

Strong physical design fundamentals, knowledgeable in timing analysis, power analysis, and scripting.

Excellent problem-solving, partnership, and interpersonal skills.
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
01/04/2024
Location: Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence.
Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.
Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects.
Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).
Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.
Ownership, self-learning skills, and ability to work autonomously.

Ways to stand out from the crowd:
Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality).
Knowledge in Tcl/Perl/Python.
Versatile.
Great teammate.
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
16/04/2024
Job Type: Full Time
We are seeking best-in-class ASIC Design Engineers to design and implement the worlds leading CPU's and SoC's. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

We are building a new group in Israel, this group will deliver security engines and risc-V processor IPs to all of our product lines working with all our groups around the world. We are looking for inquisitive, motivated engineers with experience to build this group from the ground up. As a senior member of our design team, you will be responsible for the design and implementation of high-performance, low-power security engines and risc-V processor modules. You will work closely with architects, design engineers, verification engineers, and physical design engineers to accomplish your tasks.

What you will be doing:
Participate in micro-architecture development and document specifications.

Implement in RTL and/or work on the verification team to ensure that the design is functional.

Apply logic design skills to optimize and meet performance and power goals.

Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable design.
Requirements:
What we need to see:

A Bachelors degree in electrical engineering or computer engineering.

5+ years of relevant experience in chip design development of complex designs.

Highly proficient in logic design, Verilog, and/or System-Verilog, with a deep understanding of physical design and VLSI.

Good interpersonal skills. And team player.
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
16/04/2024
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

At least 5 years of experience

Should be a power user of synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus) with 5+ years of experience.

Proficiency using Python, Perl, Tcl, Make scripting.

Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modeling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Great teammate, ownership, self-learning skills, and ability to work autonomously.

Ways to stand out from the crowd:

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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נאספה מאתר אינטרנט
27/03/2024
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for a DPU Power Modeling & U-arch senior Engineer.

We are known as a world leader in providing energy-efficient high-performance products and we continue to invest in the research and development of hyper-efficient SOC architectures. We are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional Perf/Watt solutions in a wide range of sectors and verticals. Come join our Applied Power team to develop state of the art DPU products.

What you'll be doing:

Lead Power Modeling & analysis of cutting-edge DPU technologies.

You will be contributing to power estimation models and tools for DPU products.

Work on Performance vs Power Analysis for our DPU products lineup.

Lead a micro-architecture of power management features.

Understand the workload characteristics for DPU workloads at System Scale to drive new HW/SW features for Perf@Watt improvements.
Requirements:
What we need to see:

BSc/MSc in EE or related fields with 7+ years of experience.

Strong understanding of concepts of energy consumption, estimation, data movement and low power design.

Familiarity with Verilog and ASIC design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL Architect).

Knowledge of BE flows In the field of power - a significant advantage.

Good and interpersonal skills; much collaboration with design teams is expected.

Strong coding/automation skills, preferably in Python and Perl.

Desire to bring data-driven decision-making and analytics to improve our products.
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
16/04/2024
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Act as Partition/Unit level physical design technical leader and focal point.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

2+ years of experience in physical design.

Proven experience in RTL2GDS flows and methodologies.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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נאספה מאתר אינטרנט
01/04/2024
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

At least 2 years of relevant experience.

Proficiency using Python, Perl, Tcl, Make scripting.

Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus).

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
 
נאספה מאתר אינטרנט
01/04/2024
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.

0-5 years of experience in Physical Design.

Proven experience in RTL2GDS flows and methodologies.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Deep understanding of all aspects of Physical construction and Integration.

Knowledge in Physical Design Verification methodology LVS/DRC.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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סגור
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
 
נאספה מאתר אינטרנט
27/03/2024
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

Proficiency using Python, Perl, Tcl, Make scripting.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus)

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
 
נאספה מאתר אינטרנט
01/04/2024
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.
Requirements:
What we need to see:

B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.

3+ years of practical experience.

Exposure to rtl implementation and coding.

Familiarity with verification tools.

Strong debugging, problem solving and analytical skills.

Strong communication and social skills are required.

Ability to work in a geographically diverse team environment.

Self motivated, independent and target oriented.

Ways to stand out from the crowd:

Prior Design or Verification experience.

Experience in developing sophisticated design blocks.

Integration of design elements to large cluster or full-chip.

Experience in working with back-end on area, power and timing closures.

Scripting ability.
This position is open to all candidates.
 
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
 
נאספה מאתר אינטרנט
01/04/2024
Location: Yokne`am
Job Type: Full Time
Do you want to take part in accelerating the networking solutions across our product portfolio? We're looking for a highly skilled and experienced Testing Platforms leader to provide technical expertise and management in Silicon Photonics' newly developed testing platforms on-site. The ideal candidate will ensure the smooth operation and optimal performance of the Silicon Photonics testing equipment at manufacturing sites. The Silicon Photonics Testing Platform leader will work closely with manufacturers, developers, internal teams, and other stakeholders to troubleshoot, diagnose, and resolve technical issues. This role requires excellent problem-solving skills, strong communication abilities, and a deep understanding of silicon packaging and testing methodologies.

What youll be doing:

Provide technical support and assistance to manufacturers of silicon photonics testing platforms.

Support (deployment, configure, and calibrate) semiconductor test equipment at manufacturer sites.

Manage and be responsible for the engineering documentation of the testing platforms (PDM).

Troubleshoot and diagnose technical issues related to equipment, processes, and software.

Develop practical solutions to minimize downtime and improve efficiency.

Perform root cause analysis and implement corrective actions to address recurring problems and improve the packaging process and overall systems performance.

Collaborate with cross-functional teams, including engineering, product development, and manufacturing, to resolve complex technical issues and implement system upgrades or modifications.

Develop and deliver technical training sessions for manufacturing personnel.
Requirements:
What we need to see:

Bachelors degree in electrical engineering or a related field and more than 5+ years of experience.

Proven experience working as a Manufacturing Support Engineer, Application Engineer, or in a similar role focused on silicon packaging and testing.

Strong knowledge and understanding of semiconductor packaging and testing methodologies, equipment, and processes.

Familiarity with engineering documentation systems (PDM Agile, SAP etc.).

Experience in installing, calibrating, and troubleshooting semiconductor testing equipment.

Excellent problem-solving and analytical skills, with the ability to quickly identify and resolve technical issues.

Effective communication and interpersonal skills, with the ability to work collaboratively with manufacturers and internal teams.

Strong organizational skills and the ability to manage multiple tasks and priorities simultaneously.

Willingness to travel frequently to manufacturer's sites, both domestic and international.

Ability to work independently and demonstrate a high level of initiative and self-motivation.

Ways to stand out from the crowd:

Post-silicon validation and/or customer on-site debug/FA.

experience with systems engineering.

knowledge of wafer-level testing and probing.
This position is open to all candidates.
 
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