Be part of a dynamic and motivated multi-national Physical Design team, taking part in developing a state of the art Satellite SoC through the full life cycle: design to production.
The chips include complex digital and analog modules. Some of the products are part of the next generation radiation hardened satellite modems. You will have access to best-in-class EDA design tools and will be working in leading edge process technologies.
DFT insertion of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc).
Full flow of DFT insertion: MBIST , Scan insertion , ATPG.
Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip top level.
Insertion of DFT test structures and chip level integration, capture and simulation.
Jointly with management, build your career development and growth opportunities.
Requirements: Education: At least B.Sc in Electrical Engineering, Computer Science, or related field from a major academic institute
DFT insertion flow covering: MBIST insertion, Scan chains (Compress/De-compress) insertion, hierarchical/flatten flow, ATPG generation must
SDC full support for physical team from Synthesis till full chip flatten STA must
Pattern Generation must
Tester ATE house support must
Problem-solving and analytical skills
Practical use of scripting languages Tcl/Python/Perl etc
Deep knowledge of at least one of the following EDA tool flows: Mentor (advantage)
Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow
Managing/Interfacing to sub-contract design service providers
This position is open to all candidates.