דרושים » הנדסה » Senior Memory Subsystem Architect

Requirements:
MINIMAL REQUIREMENTS
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
At least 20 years of experience in one of the leading CPU companies
REQUIREMENTS
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
QUALIFICATIONS
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
MINIMAL REQUIREMENTS:
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
Ownership of the overall verification methodology for a CPU project.
REQUIREMENTS
MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Minimum of 10 years of proven design experience in complex processor projects.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to US, Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
REQUIERD
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Good understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store units, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory controller.
Good understanding of high speed digital VLSI design flow and methodology
Understanding of trade-offs between power, performance and area appropriately to meet the requirements of the product.
At least 6 years of experience in one of the leading CPU companies
Familiarity with the ARM\IA architecture and the micro-architecture for current ARM\IA CPU cores.
Software development (C, assembly).
Hands on experience as a Front end ASIC designer
DESIRED
Co-operate and communicate well with the architecture team and other members of the development.
Excellent verbal and written communication skills.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
MINIMAL REQUIREMENTS
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Good understanding of CPU design methodology
Excellent verbal and written communication skills.
CPU related Experience in one of the leading CPU companies or in academia.
Willing to relocate to China for extended period.
REQUIREMENTS
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Experience modeling microprocessors using higher-level languages, like C/C++.

Requirements:
B.Sc. in Electrical Engineering (or equivalent academic degree)
10+ years in VLSI design (less can be accepted in case of a unique candidate).
At least 5 years as Architect.
Ability to make trade-offs between power, performance, and area appropriately to meet the requirements of the product.
Experience with AI - Mandatory.
Advantages:
Experience with High level design languages like System-c an advantage.
Hardware accelerator development.

Requirements:
MINIMAL REQUIREMENTS
At least 15 years of hands on experience as RTL/Architect of complicated SoCs
Solid understanding in SoC parts (DDR, L3 cache, GPU .)
Proven experience of owning whole SoC units/architecture
Good understanding of SW (e.g. C, C++)
Ability to make tradeoffs between power size and performance
REQUIREMENTS
At least 15 years of hands on experience as RTL/Architect of complicated SoCs
Excellent Verbal and written communication skills
Co-operate and communicate well with different groups from different countries.
Advantage:
Familiar with Core Architecture
Familiar with CPU SoC Architecture
Familiar with Mobile devices
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Experience in modelling SoC using high-level language.

Requirements:
PhD or MSc in computer science/EE or area related to computer architecture, or equivalent research experience in industry
At least 15 years of relevant research and development experience in industry and academia in the following areas:
- Computer architectures: instruction set architecture, microarchitecture, cache sub-system, memory sub-system, NOC, interconnect
- Workload characterization and analytical model generation
- System Modelling and emulation of HW
- Simulation of Software workloads and Software applications on HW simulator
Ability to provide innovation and an international vision
Excellent communication, presentation and reporting skills
Experience working with highly technical teams and communicating to non-technical partners
Excellent oral ability to provide innovation and an international vision
Excellent communication, presentation and reporting skills
Excellent oral and written English. written English.

Requirements:
Bachelor degree or higher in Computer Engineering / Computer Science or equivalent
5+ years of experience in implementation and design of SW / SW+HW systems (mainly in C / C++)
Hands on experience with compilers design and architecture
5+ years of experience developing for LLVM + Clang
5+ years of proven experience working with CPU instruction set architecture and assembly language
System view and profound understanding of related technologies
Hands-on system design and PoC bring-up experience
Excellent communications skills and ability to work as part of an international team
Innovation, fast learning skills
Ways to stand out from the crowd:
M.Sc. or Ph.D. degree with expertise in fields related to compilation / static analysis
Experience in HW + SW systems co-design
Experience with developing gcc plugins
Experience in Linux kernel modifications / kernel modules development
5+ years of experience in software development in Linux environment
2+ years of experience in optimizing applications performance
Proficiency in C++ programming language
Understanding in multiprocessing and multithreaded code.

Requirements:
Mandatory:
6+ years of experience as a software or system engineer in the field of Wi-Fi
B.Sc./M.Sc. in Computer Science, Computer Engineering, Electrical Engineering or other related field
System view and profound understanding of 802.11 protocol and Wi-Fi MAC layer
Hands-on C & C++ experience
Team player with good interpersonal and communications skills
Self-motivated and able to work independently
Advantage:
Hands-on Python experience
Experience in Linux based development environment
Knowledge or experience with network simulation tools (ns-3, OPNET Modeler etc.)
Experience with design / development of 802.11 performance oriented algorithms (e.g. high throughput, low latency, low jitter, rate selection)
Good understanding of 802.11 PHY and MAC/PHY interfaces
Good understanding and experience with IP and IP protocols (TCP, UDP, QUIC etc.).

Requirements:
PhD or MSc in computer science or area related to computer architecture, or equivalent research experience in industry
At least 10 years of relevant research experience in industry or Academia
Ability to provide innovation and an international vision
Experience analyzing performance of new application and root cause of performance bottlenecks
Candidates should have research experience in at least one of the following areas:
- Computer architectures: instruction set architecture, microarchitecture, cache sub-system, memory sub-system, NOC, interconnect
- Workload characterization and analytical model generation
- Heterogeneous Architectures and Systems for Datacenter
- Parallel, High-Performance, and Distributed Computing with an emphasis on hardware-software characterization, optimization and innovation
Excellent communication, presentation and reporting skills
Experience working with highly technical teams and communicating to non-technical partners
Excellent oral and written English.