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You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

we are looking for a ASIC Leader.
Your Impact:
Review micro-architecture specifications
Supervise verification team members and provide professional guidanc
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

Youll be joining the post silicon validation team in PHY system group as part of the silicon development .
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

We are looking for a motivated and detail-oriented Safety Laboratory Technician to join our Hardware Department lab team at our Tel- Aviv office.

The successful candidate will perform safety testing of company products in accordance with international safety standards. Comprehensive professional training will be provided as part of the role.

Key Responsibilities
Perform safety testing of company products in accordance with international safety standards.
Operate laboratory test and measurement equipment.
Set up, execute, and document safety test procedures.
Prepare clear and accurate test reports.
Maintain laboratory equipment and ensure compliance with laboratory procedures.
Work closely with engineering and regulatory teams to support product certification activities.

We are looking for a versatile Senior Software R&D Engineer and a dedicated team member to join our multidisciplinary group. This role places a heavy emphasis on hardware bring-up, low-level software development, and collaborative engineering. You will be a core player in a tight-knit team, moving seamlessly between different phases of system creation-from architecting board support packages (BSPs) and troubleshooting new hardware boards to designing high-performance application features.

Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.



Responsibilities:
Active Team Member: Collaborate daily within a diverse R&D team. Brainstorm solutions, conduct peer code reviews, and share knowledge to elevate the teams capabilities.
Hardware Bring-up & BSP: Lead the software-side bring-up of next-generation hardware. Design, develop, and debug Board Support Packages (BSPs) to seamlessly bridge the hardware-software boundary.
HW/SW Integration: Partner closely with hardware engineers to diagnose system-level bottlenecks, read schematics, and ensure optimal hardware performance.
Real-Time Feature Implementation: Design and develop high-performance software features and real-time application layers for our flagship product.
Product Implementation Design: Translate complex product requirements into scalable, highly reliable software designs and system architecture.

we are looking for a ASIC Design Engineering Technical Leader.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macro and cluster-level blocks, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsys and Cadence.
* Engaged in defining implementation and signoff methodologies.

we are looking for a Logic Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Key job responsibilities
* Design and implement advanced Design-for-Test (DFT) architectures for complex semiconductor platforms.
* Develop high-quality test and debug patterns ensuring robust performance.
* Conduct comprehensive static timing analysis across multiple DFT modes.
* Verify intricate DFT logic and components with precision and creativity.
* Support silicon bring-up and device diagnostic processes.

Your day will be filled with complex problem-solving and collaborative innovation. You'll work alongside world-class DFT engineers in a dynamic environment, developing semiconductor technologies that support global cloud infrastructure. Our team thrives on creativity, technical excellence, and continuous learning.

we are looking for a Junior Physical Design Engineer.
You'll be joining our Physical Design team , which is at the center of the silicon development . Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.
We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

Lead verification for advanced ASIC/FPGA designs in a top-tier R&D team developing high-performance network interface solutions and customer-focused hardware.

Location: Tel Aviv office or our Beer Sheva office, which is located next to the train station



Responsibilities:
Drive verification of complex, high-speed ASIC/FPGA designs
Define and implement advanced verification methodologies
Collaborate with architecture, software, and validation teams
Mentor engineers and promote technical excellence
Work with technologies like high-speed interfaces, network processors, and SoCs

We are looking for Software Automation Engineer to help us develop a semiconductor platform based on a revolutionary architecture.

Take part in the development of products within a disruptive system architecture. Youll have the opportunity to work in a dynamic, open, fast-paced environment, developing the technologies that power the worlds largest cloud provider. AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.

Key job responsibilities
As Software Automation Engineer, you'll be responsible for creating ML (Machine learning) and HPC (High performance computing) automation and tools, create CI/CD flows and implement effective dashboards with high scale.

we are looking for a Senior Physical Design Engineer.
Your Impact:
You'll be part of the team, which is at the heart of software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

we are looking for a Senior Asic Design.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab