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We are looking for a talented software engineer with a passion for security to help build innovative edge-to-cloud security solutions for our next-generation devices and platforms.

You will contribute to and lead the development of core product features, from understanding system and product requirements and defining feature behavior, through architecture, design, and implementation, to delivering high-quality, secure services and endpoint components.

You will work across the stack, spanning firmware, hardware, operating systems, and cloud-connected security solutions, helping build the trusted security foundations of next-generation devices. You will collaborate with silicon partners, security experts, and engineering teams across us to deliver innovative, end-to-end security capabilities. The role offers significant technical ownership, opportunities to drive innovation, and continuous growth at every stage of your career.

AI is a core part of how we engineer. Our team has broad access to advanced AI capabilities, including unrestricted usage with no token limits, enabling engineers to fully integrate AI into their daily workflow. We actively use AI to accelerate design, coding, debugging, security research, testing, and documentation. We also empower engineers to go beyond personal productivity by building AI-powered tools and agents that improve how the entire team works and delivers value.

Join us in pushing the boundaries of security engineering. From silicon and firmware to operating systems and cloud-connected services, you'll help build trusted foundations that secure our future devices and experiences on a global scale.


Responsibilities

Partner with product, system, cloud, firmware, hardware, and security engineering teams to design and deliver innovative security solutions.

Contribute to and lead the design, implementation, integration, testing, and delivery of core security features spanning firmware, operating systems, endpoint software, and cloud-connected services.

Develop and integrate secure, reliable, scalable, and maintainable software and services using industry best practices and our high security and engineering standards.

Apply secure engineering practices, including threat modeling, secure design reviews, code reviews, mitigation planning, vulnerability response, and security validation.

Define technical requirements, architecture, dependencies, engineering priorities, and delivery plans in a complex cross-team environment.

Work closely with hardware, firmware, operating system, Windows internals, cloud, and security engineers to characterize solutions, define interfaces, and optimize security, reliability, and performance.

Drive features from inception through production, including quality, observability, deployment, monitoring, incident readiness, and continuous improvement.

Leverage advanced AI capabilities to accelerate engineering workflows and build AI-powered tools and agents that improve team productivity and product quality.

Continuously learn emerging security technologies and attack techniques, share knowledge with the team, and mentor peers as your experience grows.

The WSSI (Windows Silicon System Integration) team is looking for an experienced Silicon Design Verification Team Lead to lead verification for complex silicon subsystems that are part of advanced solutions delivered in Windows client products.

This is an opportunity for an excellent DV leader to combine people leadership with meaningful hands-on technical contribution. You will lead a silicon engineering team that includes design verification, silicon design, and physical design engineers, while serving as the technical anchor for the team's verification strategy, execution, and quality.

The team works on complex security-oriented silicon subsystems that require rigorous pre-silicon verification and close collaboration with architecture, design, firmware, system engineering, and physical design partners to deliver robust silicon quality.

We are looking for a leader who is passionate about building excellent teams, driving rigorous execution, contributing hands-on to complex verification challenges, and continuously improving verification methodologies - including applying modern AI-assisted techniques to improve productivity, debug efficiency, and verification quality.

Responsibilities
Lead, grow, and mentor a silicon engineering team that includes design verification, silicon design, and physical design engineers, while fostering a culture of technical excellence, ownership, collaboration, and continuous learning.
Own and drive the verification strategy for complex silicon subsystems from planning through execution, closure, and emulation readiness.
Provide substantial hands-on technical contribution and leadership in verification planning, testbench architecture, debug, coverage analysis, regression quality, and verification closure.
Build and promote modern verification workflows, including AI-assisted techniques that improve verification environment development, automation, debug efficiency, coverage analysis, and execution quality.
Define verification plans, quality metrics, regression strategy, coverage goals, and emulation readiness plans aligned with project milestones.
Collaborate closely with architecture, design, system engineering, firmware, and physical design partners to identify risks early, resolve complex issues, and deliver high-quality silicon subsystems.

The WSSI (Windows Silicon System Integration) team is looking for a Senior Silicon Designer to help design complex silicon subsystems that are part of advanced solutions delivered in Windows client products.
This is an opportunity for an excellent silicon engineer to take meaningful technical ownership in a dynamic, agile, and highly collaborative environment. You will work on advanced subsystem design spanning microarchitecture, RTL implementation, integration, and design quality, with close collaboration across architecture, verification, firmware, system engineering, and physical design teams.
The role focuses on complex security-oriented silicon subsystems. We are looking for someone who combines strong design fundamentals with curiosity, ownership, and the motivation to learn and apply modern techniques - including AI-assisted workflows - to improve silicon development productivity and quality.

Responsibilities
Own and drive microarchitecture and RTL design for complex silicon blocks and subsystems, translating architecture and system requirements into clean, efficient, and high-quality hardware implementations.
Collaborate closely with verification, firmware, system engineering, architecture, and physical design partners to define interfaces, debug complex issues, manage technical risks, and deliver robust silicon solutions.
Contribute to subsystem integration, design reviews, quality checks, synthesis readiness, timing considerations, and design handoff flows.
Explore and apply modern silicon development workflows, including AI-assisted techniques for design productivity, debug, documentation, and quality improvements.
Act as a technical leader within the team by mentoring others, raising the engineering bar, and helping drive execution in a fast-moving environment.

Required Senior CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving force behind groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Design Vision Lead, Edge AI, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
Lead an edge AI IP design team across definition, implementation and deployment phases, while establishing IP development methodologies sharing unified blocks within the IP design team.
Author block-level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.

Required Senior Test Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Tests (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Responsibilities
Develop and implement high-volume manufacturing strategies for SoC products, optimizing ATE/SLT test coverage, reduce Defective parts per million (DPPM) and test costs, and manage product data integration.
Accelerate mass production via test program releases, data analytics, lot disposition, test time reduction, yield improvement, and return merchandise authorization (RMA) handling.
Partner with cross-functional teams (Test, Quality, Packaging, Operations) to deploy and maintain high-volume manufacturing (HVM) screening solutions.
Manage database integration for wafersort, final test, SLT, and burn-in, while overseeing test program integration, production release, binning, manufacturing flow definition, NPI material handling, and foundry process optimization.

Required IP Design Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System-on-a-Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high-quality SoC/RTL. You will also solve technical issues with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of our platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Own Networking Internet Protocols (IP's) Design team including definition, implementation and deployment.
Establish IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.

Required CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Senior RTL Design Engineer, Digital Signal Processing
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an RTL Design Engineer, you will be a key contributor to the physical implementation of next-generation TPU technology building ASICs for high-speed communication systems. You will take ownership of complex blocks, translating mathematical models into bit-exact silicon. Your expertise in front-end design flows will be vital in delivering the hardware that powers our advanced AI models and cloud services.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
Responsibilities
Design and implement high-speed blocks, taking end-to-end ownership of complex modules within the larger system.
Solve complex implementation issues related to GHz-frequency timing closure and advanced process nodes.
Transform high-level architectural specifications and communication theory models into efficient, bit-exact implementations.
Perform fixed-point analysis and micro-architectural trade-offs. Execute and optimize the front-end design flow for your assigned components to ensure, sign-off quality designs.
Collaborate closely with verification teams to develop bit-exact C++/SystemC models and ensure seamless integration.