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As a chip design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops some of the switch silicon core units

Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

Join us, the industry leader in high-speed communication devices, as a Physical Design Engineer in our Networking Silicon engineering team. You will develop innovative chips with outstanding efficiency and minimal latency. This opportunity lets you be part of a team leading modern technology, where your contributions will have a meaningful impact in a dynamic and inventive environment. We value collaboration, inclusion, and excellence, ensuring our technology remains world-class and our team members are supported to succeed.

What you'll be doing:

Engaging in the physical build of blocks according to specifications under challenging constraints, targeting efficient power, area, and performance.

Working on a variety of exciting builds, resolving complex timing and congestion issues with precision.

Engaging in all facets of physical chip build development (RTL2GDS), including synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Contributing to flow development to improve and innovate our processes.

Collaborating with a team of outstanding engineers to achieve flawless integration and implementation of builds.

Our Advanced Development Network Engineer role in Israel offers a special chance to contribute to large-scale network simulations for innovative AI datacenter research and development. You will be part of a dynamic team that values creativity and collaboration. If you are enthusiastic about technology and eager to build a significant difference, this is the place for you!

What you'll be doing:

Developing a brand new digital twin powered by CUDA technology for advanced research on data centers.

Collaborating with a team of extraordinary engineers and researchers to develop and implement innovative solutions.

Partnering with diverse teams to ensure smooth integration and deployment of network solutions.

Continuously exploring new technologies and methodologies to improve our network capabilities.

Imagine what you could do here. , new ideas have a way of becoming extraordinary products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Do you want to join us to help deliver the next groundbreaking Apple products?

As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and run-set development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also, you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies.
Responsibilities
Develop, improve and maintain all aspects of physical verification flow and methodology
Coordinate the effort of validating flows, improving for custom checks and data generation
Work with the design and PD teams to facilitate the chip design process
Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
Collaborate with tool vendors and foundries for PDK performance enhancements

As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our pre-silicon hardware validation efforts using Cadence Palladium emulation platforms, enabling early system integration and hardware validation. You will work closely with SoC architects, RTL designers, and verification engineers to ensure our designs are thoroughly validated before tape-out. You will help define the processes, methods, and tools for emulation environment development and debug of large complex SoCs.
If you enjoy a fast-paced and ambitious environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply and join us!
Description
Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations.
System-level debug and root cause analysis of complex hardware issues on the emulation platform.
IP-level debug and validation, working closely with IP owners to isolate and resolve design issues.
Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization.
Performance profiling and optimization of emulation models to maximize execution speed.
Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.
Responsibilities
Own and maintain Palladium emulation build flows for SoC and subsystem-level models
Drive debug and triage of emulation model issues, working with RTL designers and verification engineers
Support system-level hardware validation efforts and hardware integration
Develop reusable debug methodologies and collateral to accelerate issue resolution
Optimize emulation model performance through compile tuning, partitioning strategies, and platform configuration
Thoroughly document flows, debug procedures, and best practices
Collaborate with cross-functional teams to define emulation requirements and support prototype hardware validation

Were looking for a V&V Student to help verify that our products meet all system requirements and conform to Spec, and to validate and assure a quality competitive product that fits and satisfies the customers needs.
Reports to: Lab Manager
Location: Afek Industrial Park, Rosh Haayin
What will you do?
Execute tests on different levels (Component, Assembly, Sub-system integration, System level testing)
Perform results analysis and present them to the test owner
Perform Integration work on machines, simulation tools and jigs
Monitor and measure machine KPIs while operating the machines
Provide Feedback & troubleshoot system problems, fault recovery and accurate data transfer to the Development Department
Performs preventive maintenance routines
Take parts in upgrading R&D machines to the latest technologies.

We are seeking an experienced and hands-on engineering leader
to drive product quality, reliability, and performance across NPI, manufacturing, and the installed base. The role serves as a technical focal point for complex multidisciplinary issues, leading investigations, task forces, and improvement initiatives that enhance product quality , manufacturing readiness, and customer satisfaction.
What Will You Do?
Product Quality and Reliability:
Own product quality and reliability performance across NPI, manufacturing, and the installed base.
Define, monitor, and analyze quality metrics, reliability indicators, and field performance trends.
Consolidate quality and performance data from internal operations, contract manufacturers, and field systems into actionable insights and management dashboards.
Lead root-cause investigations and corrective/preventive actions (CAPA) for high-impact product and field issues.
Identify systemic issues, prioritize improvement opportunities, and drive cross-functional execution plans to improve product quality, reliability, and customer experience.
NPI, Manufacturing & Installed Base Support:
Drive quality and reliability readiness throughout NPI, validation, and production ramp-up activities.
Lead investigations into complex production, integration, and field failures involving multidisciplinary system interactions.
Partner with Manufacturing, Service, Operations, and Supply Chain teams to improve product stability, serviceability, and operational performance.
Drive implementation of calibration, alignment, validation, and test methodologies that improve quality, consistency, and manufacturing efficiency.
Support contract manufacturers and production teams in resolving critical technical and quality-related challenges.
Continuous Improvement & Change Management:
Lead engineering improvement initiatives based on production performance, customer feedback, reliability data, and field experience.
Drive product robustness, manufacturability, serviceability, and lifecycle performance improvements.
Own execution of Engineering Change Orders (ECOs), product structure management, and change implementation through CCB processes.
Lead periodic product performance reviews and drive closure of improvement actions across functions.