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we are looking for a Logic Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Key job responsibilities
* Design and implement advanced Design-for-Test (DFT) architectures for complex semiconductor platforms.
* Develop high-quality test and debug patterns ensuring robust performance.
* Conduct comprehensive static timing analysis across multiple DFT modes.
* Verify intricate DFT logic and components with precision and creativity.
* Support silicon bring-up and device diagnostic processes.

Your day will be filled with complex problem-solving and collaborative innovation. You'll work alongside world-class DFT engineers in a dynamic environment, developing semiconductor technologies that support global cloud infrastructure. Our team thrives on creativity, technical excellence, and continuous learning.

Lead verification for advanced ASIC/FPGA designs in a top-tier R&D team developing high-performance network interface solutions and customer-focused hardware.

Location: Tel Aviv office or our Beer Sheva office, which is located next to the train station



Responsibilities:
Drive verification of complex, high-speed ASIC/FPGA designs
Define and implement advanced verification methodologies
Collaborate with architecture, software, and validation teams
Mentor engineers and promote technical excellence
Work with technologies like high-speed interfaces, network processors, and SoCs

we are looking for a Senior Physical Design Engineer.
Your Impact:
You'll be part of the team, which is at the heart of software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

We are looking for a junior Embedded Software Engineer, to join us in building the next generation of networking products. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, fast-paced environment. Working for Annapurna Labs is thrilling and a constant learning experience. As an embedded SW development engineer, you will be responsible for developing features for Annapurna Labs next-generation hardware, to enable high network bandwidth and packets-per-seconds (PPS) performance, with consistently low latency. You will work to bring up a broad selection of instance types, optimized for various use cases, to suit each of our customers needs, such as varying combinations of CPU, memory, storage, and networking capabilities. As a SW development engineer, you will play a key role in shaping architecture definitions and SW system designs, and help to resolve complex customer issues. You will continuously evolve technically, while working to monitor AWS cloud health, maintain high quality standards, develop highly-optimized code, and provide exceptional customer satisfaction.

Key job responsibilities
We will be conducting a unique onboarding training program, where you will be studying the following with our technical experts and team leaders:
* Embedded systems basics.
* Annapurna technologies in EC2.
* Cloud compute development.
* Networking 101.

we are looking for a IC Package Design Engineer.
In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.
You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.
Responsibilities:
As a member of the Package Design team, you will:
Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing suport.
Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.
Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.
Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.
Assist in developing and improving package design methodologies, flows, and best practices.
Contribute to debugging, issue resolution, and package bring‑up activities as needed.

We are looking for exceptional engineers to join the top-tier team developing the next generation semiconductor platform based on a revolutionary architecture. You will participate in design activities, working on the next generation of our products.

As a Chip Design Engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities:
* Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

we are looking for a ASIC Engineer.
Your Impact:
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

Required Power Supply Expert
About the Role
Get a deep understanding and perfect knowledge of the project documentation, especially about the Power Supply system (High Voltage substations, Medium Voltage distribution network, Traction power simulation, Traction and Auxiliary substations) and the interfaced systems: Requirements (MDSM, Owner Requirements, Project Program), Interfaces & integration (NSA), and lists of Deliverables & Tasks (DTG).
Be able to verify the Design that the designers, called Line Managers (LM) will submit, to answer to their questions and to analyze their proposals.
Provide technical, and program feedback and advice on challenges, possible areas of improvement as well as possible alternatives, innovations.
Provide analyses of the LM designs and change proposals to perform Multiple Criteria Analyses to justify decisions for accepting or rejection.
Be able to decide to apply one LM proposal to the other lines for uniformity of the metro network, leading to reduce costs (for construction, integration, operation), to improve operation, make maintenance easier, or to enhance reliability, availability, and safety.
Carry out the studies to change some points of the metro tender documents and manage the LM to apply them.
Coordinate with the other technical disciplines (Rail Systems, CW, external stakeholders) for interfaces and be able to provide all required information for the success of the integration, Testing & Commissioning to get approval on power Supply and lead to the metro operation.
Serve as the Programs technical, process and professional expert on behalf of the Client, to make engineering decisions, accept design proposals or technical solutions, make recommendations, resolve technical clashes, etc., instruct and monitor the implementation and adherence to the Client Metro Network (MN) Power Supply documentation by Metro Line managers/designers and relevant Program participants.
Support, as necessary, the Client in providing technical support in relation to the management of Program statutory approval of designs.
Develop, when needed to be designed/procured at Network Level, the power Supply Programs reference design and/or performance specifications.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a DFT Engineer at our company, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.
Key Responsibilities
DFT Architecture & Strategy
Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices
Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools.

We are a global leader in LiDAR technology. Beyond automotive, we provide off-the-shelf LiDAR solutions for defense and homeland security, intelligent traffic management, mobility, robotics, and aerial applications. The ATE Systems Group leads the development of complex, multi-disciplinary capital equipment (software, hardware, optics, mechanics), automated machines designed for the calibration, testing and production of the cutting-edge LiDAR technology.
We are looking for a hands-on ATE system Technician to join our team.
As part of the team, youll:
* Bring-up multi-disciplinary setups & testers.
* Execute complex system integration testing and experiments.
* Support testing a variety of company's products.
* Tester validation, verification, qualification, and certification.
* Interact with multi-disciplinary systems and teams.
* Write documentation, TEST plans, and results (English).
Sub Department:
ATE
City:
Rosh HaAyin

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.
As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our companys products to operate reliably in the worlds most demanding AI and cloud environments.
Key Responsibilities
Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews.