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We are looking for a Cloud Monitoring Engineer to join our growing team and ensure our systems and customer environments are always optimized, available, and secure. This role combines proactive monitoring with incident management and operational excellence to deliver outstanding results for our customers.
Responsibilities
Proactive Monitoring: Continuously monitor our and customers environments using tools such as Kibana, Grafana and other cloud monitoring solutions.
Investigate and respond to application, system, and network issues to ensure maximum service availability.
Identify and troubleshoot anomalies in production and staging environments powered by AWS, GCP, Azure, Kubernetes, Docker, and EKS/ECS.
Document and categorize incidents, reporting them accurately.
Collaborate with cross-functional teams (TS, R&D, Product) to address and resolve underlying issues.
Communicate changes, updates, and improvements effectively within the organization.
Develop and enhance monitoring methods, tools, and automation processes.
Stay updated on emerging technologies in cloud monitoring and security to ensure best-in-class solutions.

We're looking for a curious, fast-learning individual for a student role on our Product team to help enhance user experiences through effective design practices. In this role, you'll work closely with other Product Designers in your team, with the guidance of the team lead, to participate in the design process, research, ideate, shape, and innovate complex products.
What youll do:
Support design work across assigned product areas
Participate in the design cycle from research and ideation to prototype and delivery
Create wireframes, prototypes, and visual deliverables as coherent design concepts
Collaborate with stakeholders to help review design implementation and flag issues
Help maintain the design system, ensuring alignment across various projects
Scale the design system, creating components using Figma and Claude Code
Conduct design research on a variety of topics, from competitors to styling trends
Contribute to enriching the brand design language, creating assets with AI tools.

we're seeking a visionary ASIC Design Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As an ASIC Design Student, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.



Key Responsibilities

Assist in the development of micro-architecture, RTL coding, and debugging for complex digital blocks
Utilize industry-leading EDA tools (Lint, CDC, Synthesis) to ensure designs are robust and power-efficient
Work closely with the verification team to run simulations, analyze results, and ensure design quality
Interact with Architecture and Backend teams to understand the full chip development lifecycle
Help leverage AI-based automation tools to optimize engineering workflows

we're seeking a visionary Design Verification Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As a Design Verification Student, you will be at the forefront of quality, learning how to ensure that the chips powering the world's largest AI clusters are bug-free and robust.
This isn't just about running tests - its an opportunity to learn advanced verification methodologies (UVM/SystemVerilog) alongside world-class engineers. You will support the development of sophisticated testbenches and help verify high-performance digital blocks that sit at the heart of AI infrastructure.



Key Responsibilities


Assist in building and maintaining System Verilog/UVM-based testbenches, including monitors, checkers, and functional coverage models
Run simulations, analyze failures, and work with the design team to debug and resolve RTL issues
Help define and implement functional coverage and assertions to ensure all "corner cases" of the design are tested
Utilize and improve scripting (Python/Tcl) to streamline verification flows and result reporting
Partner with Design Engineers to understand block specifications and ensure the verification plan matches the design intent