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We are looking for exceptional engineers to join the top-tier team developing the next generation semiconductor platform based on a revolutionary architecture. You will participate in design activities, working on the next generation of our products.

As a Chip Design Engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities:
* Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

We are looking for exceptional software engineers to help develop the next generation chips based on a revolutionary architecture.
In this job you will design and develop software for functional and performance validation.

In this role you will develop system level software, targeting chip architecture, functional correctness and performance, running on various platforms and validating chip functionality.

We are looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.
Take part in the development of state-of-the-art products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the world's largest cloud provider, in a dynamic, open, and fast-paced environment.

We are looking for talented engineers to join our Chip Design team, working on the Graviton product line. Our chip design team is in charge of defining the product's features and working on their architecture and development. Our team members collaborate with multiple teams from different disciplines such as product definition, pre and post silicon validation, physical design, software and others contributing to a full cycle of chip development from idea to mass production. Your design will be integrated into the Graviton products, an important part of the AWS data centers worldwide. This is an opportunity to have a large-scale impact.

Key job responsibilities
Own a domain or sub-domain within an SoC - Take full responsibility for its entire lifecycle: Architecture and micro-architecture definition Writing RTL code in Verilog. Supporting the Verification and Emulation teams with test planning, debug, and results review Ensuring the final chip meets quality and reliability standards Collaborating with cross-functional teams - Partner with Product Definition, Verification, Emulation, Software, and Silicon Integration teams to deliver cohesive solutions.

We are looking for engineers to join our Pre-Silicon Verification team - the team that sits at the very center of the chip development lifecycle.

As a CPU Verification Engineer on the Graviton team, you will be responsible for verifying the correctness, performance, and robustness of our next-generation ARM CPU cores and their surrounding subsystems. You'll work at the intersection of micro-architecture, system architecture, and software - ensuring our CPUs meet the highest quality bar before they reach silicon.

Are you passionate about systems programming at the intersection of hardware and software? Do you want your code to directly accelerate the world's largest AI training and inference workloads? The Elastic Fabric Adapter (EFA) Drivers team is looking for Software Development Engineers to design and implement the kernel drivers and userspace libraries that power high-performance networking for AWS's AI/ML and HPC infrastructure.

EFA is the custom network interface that enables thousands of GPUs and accelerators to communicate at near-wire-speed bandwidth and low latency, making it a critical enabler of both foundation model training and real-time inference serving at unprecedented scale. When customers train the next generation of large language models or serve billions of inference requests with tight latency SLAs on our EC2 P5, P6, or Trn instances, it's our driver stack that moves the data.

Key job responsibilities
- Design, develop, and optimize Linux kernel drivers (RDMA/EFA) and userspace provider libraries (rdma-core) that ship to millions of EC2 instances.
- Work directly with custom hardware - collaborate with chip designers to bring new silicon capabilities to life in software.
- Contribute to the upstream Linux kernel RDMA subsystem and rdma-core open-source project.
- Architect solutions for next-generation networking features: GPU-direct RDMA, adaptive routing, collective offloads, and multi-path transport.
- Build monitoring and automation tools to enhance driver testing for functionality, reliability, and performance.
- Own the full lifecycle: from initial hardware bring-up and feature enablement through testing, deployment, and production troubleshooting across the global AWS fleet.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary System Validation Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
Job Description
The mission of this role is to perform system validation for our companys highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.
You will be part of the site located at Israel (Haifa - Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey at our company Labs Israel.

we are looking for a Software Team Lead.
As the Team Lead, you will manage a high-impact squad dedicated to ensuring compliance with critical processes and data integrity. Your role is central to driving quality, scalability, and accountability in processes such as compliance audits, credit bureau furnishing, and legal automation. This is an exciting opportunity to work at the intersection of technology, compliance, and data. You will lead Backend Engineers and Data Engineers to build robust systems that power regulatory functions. You will have the chance to shape the technical strategy and build the team (hiring and mentoring), while remaining hands-on with modern technologies.
Key Responsibilities:
Manage and mentor a dynamic team of 3 engineers (Backend & Data), fostering collaboration and professional growth. You will also be responsible for hiring and onboarding new talent to the team.
Architect scalable, high-performance systems that support compliance-critical operations. You will define the technical roadmap and drive modernization efforts.
Design and oversee both Backend infrastructure and Data Pipelines to ensure accurate, auditable, and scalable compliance processes.
Act as the single point of contact for legal and compliance stakeholders, handling and facilitating all technical aspects of audit requests (SOC, state, and other regulatory audits).
Collaborate with cross-functional teams, including other engineering teams, product managers, legal, and business stakeholders, to align technology and compliance goals.
Remain active in the codebase, ensuring high code quality and leading by example.