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Required Senior CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

we are looking for a Hardware Test and Product Engineer.
The Test & Product team is responsible for keeping a target of a very aggressive cost limit of the production testing (wafer sort) while performing comprehensive testing of all the units functionalities. This involves:
Development of the tests using the Teradyne UF tester
Development of unique and advanced test HW
Monitoring and analyses the production data
FA (Failure Analysis) when issues are discovered
Innovative DFT (design for testability) with the design team

Required Senior Staff DSP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the architect for high-speed data paths, you will define the roadmap for scaling interconnect speeds. You will evaluate and select key technologies such as Co-Packaged Optics (CPO), advanced modulation formats, and new Forward Error Correction (FEC) methods to support future Artificial Intelligence (AI) computing clusters.
Responsibilities
Identify the "limits of physics" for current Digital Signal Processing (DSP) architectures and pivot the team toward next-generation solutions, such as Machine Learning (ML)-based equalization or Optical-specific DSP.
Define the requirements for DSP test chips to validate new architectures in advanced nodes before they hit production.
Drive the long-term power-reduction roadmap, ensuring our interconnects do not become the thermal bottleneck.
Represent us in the Optical Internetworking Forum (OIF) and Institute of Electrical and Electronics Engineers (IEEE) standards, ensuring our hyperscale requirements for latency and power are reflected in global specifications.

We are seeking a senior communication systems engineer to help develop the next generation of algorithms and standards that power this revolution.

We are looking for a brilliant system engineer to join Wiliot and help to scale the world of IoT.
As a system engineer, you will work on various innovative fields from RF automation, algorithms., channel usage optimizations, energy consumption optimization and dynamic network development.

Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Cloud customers, and billions of users worldwide.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our services (Search, YouTube, etc.) and Cloud. Our end users are Googlers, Cloud customers and the billions of people who use our services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Required Senior SOC Performance Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of our AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Validate performance and power models from the architecture team and lab measurements against established goals, exercise open source benchmarks, analyze the results, and identify optimization opportunities.
Design and build tests to verify SoC design meets targets, and implement advanced technologies for running "benchmark representations" on pre-silicon environments.
Analyze problems to identify core design weaknesses, and drive resolution of performance issues in both pre- and post-silicon environments.
Collaborate closely with design, validation, and architecture teams to ensure hardware and software designs interface correctly and deliver products.
Develop performance measurement frameworks, including Key Performance Indicators (KPIs), to produce regular reports and dashboards that support stakeholder decision-making, and drive efforts to productize features that improve performance and power characteristics.

we are looking for a Senior Machine Learning Engineer to work on LLM-based systems with a strong emphasis on integration, end-to-end workflows, and production readiness. This role combines performance optimization (prefill/decode, throughput, latency) with hands-on work integrating components across the AI platform.
A significant part of the role involves building end-to-end integration flows and tests, particularly around token generation pipelines and system orchestration, as well as contributing to intelligent system behavior such as hardware selection and execution strategies. The role also includes developing system-level logic in Python for multi-tenant management, caching strategies, and service lifecycle management across the platform.
***This is not a Data Science position***
Responsibilities:
Build and maintain end-to-end integration flows across the AI inference pipeline (serving, orchestration, APIs, and infrastructure)
Design, implement, and optimize LLM inference workflows, including prefill and decode stages
Improve system performance with focus on throughput, latency, and interactivity
Write production-grade components in Python and integrate them into the broader system
Contribute to system-level logic such as smart hardware selection and execution strategies
Integrate models (open source and custom), services, and APIs into cohesive, reliable end-to-end application pipelines

we are seeking a Lead System Architect to join our system architecture team and help define the next generation of our AI-SuperNIC scale-out chip.
AI scale-out communication is a critical element in modern data centers, and emerging standards such as Ultra Ethernet aim to address this challenge. This role focuses on defining a high-performance Smart NIC architecture optimized for GPU-centric AI workloads, with emphasis on low-latency, high-bandwidth data movement.
You will work across hardware and software domains, collaborating closely with AI, platform, driver, and VLSI teams to design a competitive scale-out networking solution.
Responsibilities:
Define product requirements and architecture for next-generation ultra low-latency AI-SuperNIC
Design end-to-end data paths across NIC, host, and GPU memory, with focus on GPU connectivity (PCIe, NVLink, CXL)
Lead adoption of emerging standards such as UEC and UALink, while maintaining compatibility with existing ecosystems
Establish architecture guidelines and partitioning across hardware, firmware, and software
Drive performance modeling, analysis, and system-level optimization for AI workloads
Optimize scale-out communication patterns (e.g., collectives) for GenAI training and inference
Collaborate with software teams on drivers, runtimes, and integration with AI frameworks
Work with R&D, CTO, and peer architects on system definition and trade-offs
Engage with customers and partners to shape system requirements and use cases

The Asia EMS Project Manager is responsible for managing and controlling all operational aspects of the companys EMS partners in Asia. This is a hands-on, execution-focused role, serving as the primary operational interface between ACS and its Asia-based EMS subcontractors. The role ensures accurate planning, reliable execution, on-time deliveries, and fast resolution of operational, technical, logistical, and commercial issues, in close collaboration with internal stakeholders. Key Responsibilities
* Serve as the primary point of contact with Asia EMS subcontractors for all operational issues, including supply chain, commercial, quality, procurement, technical, IT, and logistics topics.
* Build and maintain forecasts and production plans aligned with company demand.
* Own and control the EMS production plan, ensuring execution against agreed schedules and delivery commitments.
* Identify gaps and risks and drive corrective actions to closure with EMS functions.
* Coordinate and lead resolution of cross-functional issues together with internal teams, including Engineering, Quality, Supply Chain etc.

This position is part of the global ACS Control, Support, and Applications team providing control algorithms & applications development and advanced Technical Support for ACS motion control products. Reports to: VP Control, Support and Applications
Primary Duties and Responsibilities:
Stay tuned with recent advancements in ML and incorporate innovative ideas in development of state-of-the-art control technologies for ACS products.
Custom control algorithms development for ACS customers.
Work closely with high-tech equipment manufacturers in the fields of Semiconductors, Mobile Devices and Flat Panel Displays, Life Sciences, Photonics, and more.

Primary Function of Position: Lead New Product Introduction (NPI) processes, transitioning new products from development to production, while meeting quality, cost, and schedule targets. Roles and Responsibilities: Manage and lead NPI projects from development through mass production Coordinate cross-functional interfaces: Engineering, Manufacturing, ATE, Quality, Procurement, Logistics, and Marketing Build project plans, track milestones, and manage risks Manage subcontractors for NPI manufacturing Lead end-to-end transfer processes from development to production (Transfer to Production) Drive process improvements and implement work methodologies Ensure compliance with quality and cost targets

> Design and development of complex anlog & digital boards for Motion Control applications > Participate in the architecture design of future applications and products > Support existing designs, implement changes and reliability improvement enhancements, test and validate new designs Primary Duties and Responsibilities > Design and develop complex boards > Define Requirements, engineering specs and Validation documents > Select major components, lead layout and placement using contractors > Perform Bring-Up tasks, validate design, support transition to manufacturing, support the boards in their life cycle