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נאספה מאתר אינטרנט
לפני 9 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
Our Switches ASIC group is seeking a top-tier ASIC technical manager to lead the development of our next-generation ASICs. Join us in shaping the future of technology! As an ASIC Project Lead, you will manage the pre-silicon development activities of our most advanced and complex switch ASICs. From concept to tape-out and from chip power-on to mass production, you will be the driving force behind the entire lifecycle of our ASIC projects. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams.

What youll be doing:

Development Management; Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out.

Post-Silicon Activities; Oversee chip power-on, bring-up, quality phases, and mass production.

Execution Plans; Define and implement execution plans in collaboration with cross-discipline leaders in unit level, full-chip, physical design, and firmware/software emulation.

Roadmap Definition; Contribute to the definition of our switch ASIC roadmap.
Requirements:
What we need to see:

BS or MS in Computer or Electrical Engineering or equivalent experience.

12+ overall years of proven experience in chip design.

4+ years of experience in chip design/verification management, leading teams of at least 8 direct reports.

Proficiency in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation.

High system view with ability to collaborate with multiple interfaces.

Strong analytical and problem-solving skills.

Excellent communication and teamwork abilities.

Experience in synthesis, and physical design is a plus.
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
06/10/2024
Location: Tel Aviv-Yafo
Job Type: Full Time
Our Switches ASIC group is seeking a top-tier ASIC technical manager to lead the development of our next-generation ASICs. Join us in shaping the future of technology! As an ASIC Project Lead, you will manage the pre-silicon development activities of our most advanced and complex switch ASICs. From concept to tape-out and from chip power-on to mass production, you will be the driving force behind the entire lifecycle of our ASIC projects. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams.

What youll be doing:

Development Management; Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out.

Post-Silicon Activities; Oversee chip power-on, bring-up, quality phases, and mass production.

Execution Plans; Define and implement execution plans in collaboration with cross-discipline leaders in unit level, full-chip, physical design, and firmware/software emulation.

Roadmap Definition; Contribute to the definition of our switch ASIC roadmap.
Requirements:
What we need to see:

BS or MS in Computer or Electrical Engineering or equivalent experience.

12+ years of proven experience in chip design.

4+ years of experience in chip design/verification management, leading teams of at least 8 direct reports.

Proficiency in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation.

High system view with ability to collaborate with multiple interfaces.

Strong analytical and problem-solving skills.

Excellent communication and teamwork abilities.

Experience in synthesis, and physical design is a plus.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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7895633
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נאספה מאתר אינטרנט
23/10/2024
Location: Tel Aviv-Yafo and Herzliya
Job Type: Full Time
Specifying requirements and circuit architecture for analog blocks and sub-blocks of an IP, lab bring-up, characterization and debug, write specifications, test plans and characterization reports, work with chip design teams, system HW and SW design teams, ATE PE.

You will be responsible for:
Develop the circuit design of the IPs analog blocks following established design guidelines based on microarchitecture spec. Own all aspects of circuit design development.
Work and collaborate with other designers in the group to deliver results.
Work with FE & BE teams to ensure quality analog integration.
Work with power/performance and functional verification team to define and validate operation sequences.
Work with multi-disciplinary teams to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.
Work with post silicon validation groups to ensure the design meets the power/performance targets.
Requirements:
Minimum Qualifications
5+ years experience in analog IC design.
Deep understanding of transistor device characteristics.
Deep understanding of power, performance and area trade-off in mixed-signal designs.
A proven track record of high-performance designs in high volume production for low power applications.
Knowledge of analog IC design flow and tools.
Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company.
Excellent social and interpersonal skills.
Hands-on design expertise in one or more of the following areas: High Speed, Low Power I/O Circuit Design: familiarity with PHY principles and concepts including forwarded clock topologies, training and calibration schemes etc.); High Speed Clock Path: low jitter distribution, DCD correction, phase shift (through delay lines or phase interpolation); Analog Front End: low noise and high-resolution signal conditioning prior to ADC and Op-Amp, switched-cap and continuous time filters, reference/bias generation, LDO etc.; Data Conversion: ADC and DAC subsystem. Different styles of data converters (ΔΣ, SAR, pipelined, SAR and flash) and associated calibration techniques.
Strong initiative and ownership of responsibilities, productive.
Ability to work well in a team and be productive under tight schedules.
Experience with advanced FinFET CMOS processes - an advantage..
Preferred Qualifications
- BS.c in Electrical Engineering.
- MS.c\ PhD - advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
7912267
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נאספה מאתר אינטרנט
2 ימים
Location: Rehovot
Job Type: Full Time
Required Physical Design Engineer (Backend)
Job Description:
Be part of a dynamic and motivated multi-national Physical Design team, taking part in developing a state of the art Satellite SoC through the full life cycle: design to production. The chips include complex digital and analog modules. Some of the products are part of the next generation radiation hardened satellite modems. You will have access to best in class EDA design tools and will be working in leading edge process technologies.
Physical implementation of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc)
Full block level timing closure and manufacturing checks signoff including power planning and analysis
Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip level
Insertion of DFT test structures and chip level integration, capture and simulation.
Requirements:
At least B.Sc. in Electrical Engineering, Computer Science, or related field from a major academic institute.
COT/ASIC physical design flow covering: Synthesis, Floorplanning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure, Physical Verification, Power Analysis, Formal Verification, DFT/DFM and ATPG insertion/pattern generation
Deep sub-micron (28nm or below) process technologies
Industry standard design processes for deep sub-micron designs
Problem-solving and analytical skills
Practical use of scripting languages Tcl/Python/Perl etc
Experience of at least one of the following EDA tool flows: Cadence or Synopsys
Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow
Managing/Interfacing to sub-contract design service providers.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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7917523
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