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Tavily team is building the search engine for AI agents. We believe the future of work will be led by AI agents, and that requires restructuring how the web is accessed. Our Search API provides web access for AI agents, enabling real-time internet search optimized for LLMs and Retrieval-Augmented Generation (RAG). We are backed by leading investors and serve developers and enterprises worldwide. Our team is fast-moving and ambitious. We ship quickly, iterate constantly, and care deeply about impact.
As a Software Engineer - Scraping Specialist, youll build the systems that power how AI interacts with the live web. Youll design and implement large-scale, intelligent web acquisition pipelines, making sense of an ever-changing online ecosystem and transforming it into structured, high-quality data.
This role blends technical understanding of browsers, networks, and automation with hands-on engineering. Youll work on adaptive systems that navigate modern websites, understand evolving web interaction ,detection systems, and gather meaningful information safely, efficiently, and at scale.
Your work will directly shape Tavilys ability to provide AI agents with accurate, real-time knowledge of the world , bridging the gap between the open web and intelligent reasoning.
What Youll Do
Build distributed data acquisition systems that capture and structure the live web
Investigate and analyze browser internals, fingerprinting, and anti-automation systems to develop stealthy, adaptive orchestration layers
Prototype and deploy intelligent automation frameworks using Playwright, Puppeteer, and low-level browser control protocols (CDP)
Conduct hands-on research into network flows, JavaScript-based protections, and emerging web standards affecting automation
Collaborate with AI and infrastructure teams to integrate real-time web data into retrieval pipelines and LLM-powered agents
Translate deep technical insights into production-grade components, balancing research freedom with engineering rigor
Continuously evolve Tavilys capabilities in resilience, speed, and authenticity of web interaction.

At our company we are passionate believers in the value and power of 3D printing, and in the change, it can bring to design, innovation and manufacturing.
The solutions we create are used by over 20,000 enterprises worldwide, and we literally are shaping the world that surrounds us - from the products and services in our lives and homes, to our health and quality of life, our transport, security and economies, to how we teach, research and even learn.
we are the world's largest 3D printing solutions company - a company at the forefront of 3D printing innovation for more than 25 years.
Who are we looking for?
We are looking for an intelligent, well-rounded and enthusiastic Algorithm Engineer to participate in the design, development and delivery of our innovative software solutions.
The position is based in our Rehovot, Israel headquarters.
If you can operate in a team but also a motivated individual, read on
Remember that exact job descriptions never fit the bill 100% - if youre good, passionate and love to build great products, we want you.
We see your role as
Developing the infrastructure and framework for a highly scalable, Image Processing/geometry ( OpenCV, Ipp) component of a large software product.
Designing and delivering CAD to Print algorithms
Developing geometry-oriented software
Being a part of a talented team.

We are looking for a highly skilled SW developer Expert with substantial Object-Oriented experience in a multi-disciplinary environment to join our R&D group in Israel (Rehovot).
You will be a part of a talented software team that is currently developing the next generation of 3D printers, using cutting-edge technology and constantly looking for new ideas and improvements.
What you will be doing:
Lead development tasks through all stages - gathering requirements, designing, implementing (mostly using C++ and C#) and following integration on the 3D printers themselves.
Work closely with System and HW engineers, SW developers, QA and many more.
Perform design and code reviews
Constant collaboration and knowledge sharing with the SW team.

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As an Expert EMIR & Power Integrity Lead, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will own from block level to full-chip the Electro-Migration and IR Drop (EMIR) methodology, analysis, and sign-off, working at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

You will be responsible for defining power grid architectures and validating that products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes. Your work will directly impact the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities

Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews

we are leading the global shift to additive manufacturing with innovative 3D printing solutions for industries such as aerospace, automotive, consumer products and healthcare. Through smart and connected 3D printers, polymer materials, a software ecosystem, and parts on demand, our company solutions deliver competitive advantages at every stage in the product value chain. The worlds leading organizations turn to our company to transform product design, bring agility to manufacturing and supply chains, and improve patient care.
As part of this role you will:
Provide on‑line engineering support and resolve mechanical/technical issues fast.
Improve yield, cycle time, labor efficiency, and overall production performance.
Maintain and optimize work instructions, documentation, tooling, and fixtures.
Support NPIs/EOL and collaborate with cross‑functional teams, subcontractors, and partners.
Reduce rework and scrap and lead second‑source qualifications to strengthen quality and supply resilience.

As a Physical Design CAD Lead, you will be responsible for the physical implementation environment. Your primary mission is to build, optimize, and support the automated flows from RTL to manufacturable GDSII tape-out. You will own the flows, Database and will support the whole PD team to optimize their blocks for Power, Performance, Timing while keep the team aligned on Methodical, Efficient and balanced work Environment.


Key Responsibilities

Design and maintain automated flows for Synthesis, Place & Route, and Floor-planning
Develop robust environments for Static Timing Analysis, Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write custom plug-ins and scripts to extend the capabilities of vendor tools, tailoring them to our specific process node constraints and flows
Create automated "dashboards" and feedback loops to help design teams track and improve Power, Performance, and Area metrics across iterations
Collaborate with EDA vendors (Synopsys, Cadence, Siemens/Mentor) as consulters for our developed flows and results analysis     

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the worlds largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

SoC Top level Ownership and oversee the Chip convergence.
Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we're seeking a visionary Physical Design Subsystem (Multiple IPs/Partitions) Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As the Physical Design Subsystem (Multiple IPs/Partitions) Lead you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SubSystem with your team for chips that drive the worlds largest AI clusters. You will lead the team and the transition from RTL to GDS, ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

Build and mentor a high-performing Partitions team , owning the end-to-end execution from Synthesis to Signoff
Take full ownership of Subsystem physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Lead and guide external contractors and global partners to ensure seamless execution and delivery
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation

Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization

Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration

Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration

As a Senior DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy

Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Define DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies
Test Pattern Development & Optimization

Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation

Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation

Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
System-Level Debug & Validation

Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently
Cross-Functional Collaboration

Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies