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Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.



Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Spectrum-X is our ethernet networking solution for massively scaled AI factories. As a network engineer in the Spectrum-X Integration Engineering team, you will ensure that the solution's software features are developed, tested and delivered to meet the high standards of our customers. Do you want to help create the most exciting solutions in the world of networking today? If so, read on.

What you'll be doing:

Engaging directly with our customers to ensure we are aligned on their networking requirements.

Coordinating with a cross-disciplinary team of architects, testers, customer managers, and other software teams to deliver products and features on time.

Defining and reviewing switch architectures and test plans.

Providing expertise on ethernet networking both internally and to customers.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced AI models such as GPT and DeepSeek. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:
Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
Research various of solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.
Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

Are you ready to be part of a team that's pushing the boundaries of technology and innovation? At NVIDIA, we're leading the way in transforming computer graphics, PC gaming, and accelerated computing. We're now beginning the next era of modern AI computing. As a Backend Chip Integration Engineer, you will play a crucial role in building the future of our powerful technologies. This is an outstanding opportunity for those who are passionate about VLSI physical design and automation flows.

What you'll be doing:

Define chip interface and silicon interposer interface, focusing on their physical location and netlist.

Develop automation flows for chip integration and power grid implementation.

Perform power integrity analysis of the interposer power grid to ensure flawless performance.

Collaborate with cross-functional teams to successfully implement world-class solutions.

Contribute to the continuous improvement of our integration processes with your innovative ideas and expertise.

We are seeking a dynamic and highly motivated Senior Software Manager to lead our software verification and automation for DOCA Networking SDK. We are looking for a candidate who can excel in a sophisticated, multidisciplinary environment, take ownership, and drive high-quality verification and automation processes. This position offers the opportunity to have a real impact on sophisticated, groundbreaking products, delivered by us and developed by our customers, empowering the most advanced data centers in the world. This role requires close collaboration with teams across various fields (SW, HW, QA) to elevate our product to the next level.

What you'll be doing:

Lead teams of software verification engineers, providing technical direction, career development, and performance mentorship.

Define and continuously refine our software testing methodology and processes.

Engage in a hands-on approach, actively participating in the design, coding, and debugging of verification tests and infrastructure alongside your team.

Lead the verification process, ensuring the functionality, stability, and performance of our DOCA networking SDK and the solutions on top of it.

Work closely with internal and external customers to understand system use cases.

Analyze coverage measures to identify verification gaps and provide data-driven insights into product development and release readiness.

We are looking for a phenomenal engineer to join the chip simulation team for networking chips and GPUs.

This simulation platform enables our engineers across firmware, SDK, and OS domains to develop and test their code without relying on physical hardware. If you're a creative, self-driven engineer passionate about systems-level design and eager to build technology that empowers internal teams, we want to hear from you.

What Youll Be Doing:
Develop and maintain simulation components for the physical layer of our high-performance networking chips (e.g., GPUs, switches, NVLink, Ethernet...).
Collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex physical-layer behaviors in software.
Define, implement, and validate simulations of features such as link training, error injection, and transceiver behavior, making the simulation platform a go-to internal platform for development and debugging.
Extend and optimize the simulation infrastructure by contributing to CI pipelines, automated test frameworks, and regression tools.
Support internal users by debugging simulation flows and collaborating on bug resolution.
Take part in future-facing innovation by enabling simulation for next-generation devices and features.

We are looking for a Senior Signal & Power Integrity Engineer. We work closely with NVIDIA sites in USA and China and have access to extensive knowledge, technologies and tools. Yet we are responsible for our own product line of PHY ICs . Taking the products from concepting, through design, implementation, verification and release to customers. If you thrive working with highly skilled people that enjoy reaching challenging goals then NVIDIA in might be the perfect workplace for you. This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle !

What you'll be doing:

Design high frequencies channels up to 400Gb/s per lane for PCBs, packages, connectors and cables.

Design layout guidelines for our systems.

Simulate passive and active elements in 3D and 2D simulation tools.

Measure systems in the lab using Network Analyzer, TDR and scope.

Master InfiniBand, Ethernet and PCI-Ex Layer 1 specifications and implementation methods.

Work in an intense environment and control multi-discipline expertise.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

We seek a highly motivated Network Performance Exploration Engineer to join our team of experts and help shape the foundational infrastructure for the AI revolution. Our next-generation networking systems are at the forefront of connecting and powering the world's most advanced AI clusters. As a key member of our architecture team, you will be responsible for exploring and identifying critical network optimization opportunities across our entire hardware and software stack, analyzing how system-level changes impact application-level performance.

What Youll Be Doing:

Explore and validate end-to-end application performance, defining comprehensive test plans and critical metrics to identify optimization opportunities in both hardware and software.

Establish and maintain a comprehensive database of benchmark results, tracking performance across releases to drive data-informed decisions.

Conduct deep-dive analysis into communication libraries (like NCCL), system software, and hardware configurations to investigate performance characteristics, validate architectural theories, and identify bottlenecks.

Provide critical performance data to correlate and enhance simulation tools, ensuring our models accurately predict real-world hardware behavior.

Analyze application-level traffic patterns (e.g., LLMs) on our advanced networking fabrics to identify hardware and software optimization opportunities and tune system parameters.

Lead Proof-of-Concept (POC) projects to prototype and evaluate potential hardware and software optimizations and their impact on application performance.

We are looking for a best-in-class Chip Design - HW Emulation Senior Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in emulating our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. Join NVIDIA's world-class emulation team in Israel. Our focused team takes Switches/NICs/SoCs designs and program the emulators to behave like our silicon. Are you ready to take on interesting problems and craft solutions? Come check out our team.

What you will be doing:

The main responsibility is emulation and prototyping of complex chip designs. This includes defining the methodology and crafting the infrastructure needed to quickly take large chips into hardware emulation platforms.

The job also requires close collaboration with design, verification, and software engineers to enable embedded software and application software development.

Connecting emulator/FPGA based solutions to real external H/W or virtual targets, taking care of complex testbench and different protocols.

This is a role for a versatile engineer that includes RTL design, verification, FPGA partitioning and implementation, scripting, and lab-based bring up of the design.

We are seeking a dedicated NVLink Firmware Architect to join our esteemed engineering team in Israel. This is an outstanding opportunity to impact the future of data centers and networking technology. As a key member of our team, you will play a crucial role in developing and crafting our NVLink firmware stack and GPU scale-up networking. Our collaborative environment, combined with ambitious goals, will enable you to collaborate closely with ASIC and software architecture/design teams to pioneer innovative solutions.

What you'll be doing:

Lead design of new networking applications to craft new networking applications that address sophisticated problems in groundbreaking ways.

Identifying and evaluating new technologies, innovations, and partner relationships to align with our strategic technology roadmap and enhance business value.

Defining the architecture of NVLink firmware running on GPUs and switches, ensuring flawless integration and performance.

Helping to determine and implement the strategic vision for our networking alongside adjacent software and hardware architects.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

We are looking for outstanding STA (Static Timing Analysis) Physical Design Engineers to join our remarkable Networking team in Israel. Our team focuses on building the industry's top high-speed communication devices, providing the highest efficiency and minimal latency. As part of NVIDIA, you'll be working in a meaningful, growing, and highly professional environment where your contributions make a significant impact. If you are ambitious, innovative, and ready to compete on the cutting edge of technology, this is the perfect opportunity for you!

What you'll be doing:

Perform advanced Static Timing Analysis (STA) at a chiplet and FC level.

Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.

Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.

Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.