לוח משרות דרושים מהנדס חשמל בתל אביב יפו

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Our Switches ASIC group is seeking a top-tier ASIC technical manager to lead the development of our next-generation ASICs. Join us in shaping the future of technology! As an ASIC Project Lead, you will manage the pre-silicon development activities of our most advanced and complex switch ASICs. From concept to tape-out and from chip power-on to mass production, you will be the driving force behind the entire lifecycle of our ASIC projects. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams.

What youll be doing:

Development Management; Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out.

Post-Silicon Activities; Oversee chip power-on, bring-up, quality phases, and mass production.

Execution Plans; Define and implement execution plans in collaboration with cross-discipline leaders in unit level, full-chip, physical design, and firmware/software emulation.

Roadmap Definition; Contribute to the definition of our switch ASIC roadmap.

We are seeking an enthusiastic individual to join our DOCA NVQual team for Data Processing Units (DPUs) and ConnectX (CX) as a Junior Software Engineer. In this role, you will have the opportunity to learn and contribute to various features related to our product integration for AI cluster systems, helping to develop the next generation of advanced data centers worldwide.

What you'll be doing:
Work on NVQual (our Qualification), a software validation package for our partners to integrate enterprise products into their systems.
Analyze next-generation AI systems from NVIDIA and its partners, focusing on HW integration aspects.
Design and develop system workloads.
Be responsible for the end-to-end development of features within the DOCA NVQual framework.

Our networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AIs Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!

We're looking for a hardware u/architect for our switch division. In this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both Ethernet and InfiniBand. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design and platform teams to improve performance and debug.

What you'll be doing:

Learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and verification engineers.

Define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.

Define the implementation of debug capabilities to support performance validation and improvements

Understand our system requirement and help define the POR of our switch product line.

Face the most challenging Full-Chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.

Work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.

Thoroughly understand Ethernet, InfiniBand and NvLink protocols.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for a DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take ATPG ownership on different DFT aspects of a project, Arch & planning, pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

Our technology has no boundaries! We are building the worlds most groundbreaking and state of the art compute platforms for the world to use. Its because of our work that scientists, researchers and engineers can advance their ideas. At its core, our visual computing technology not only enables an outstanding computing experience, it is energy efficient! We pioneered a supercharged form of computing loved by the most fast paced computer users in the world - scientists, designers, artists, and gamers.

We are now looking for a motivated engineer to use creativity and problem solving skills to work on the ConnectX network adapter and Bluefield Data Processing Unit with the highly inventive and knowledgeable team.

What you'll be doing:

Be part of the team that defines the Network Interface Card (NIC) and Data Processing Unit (DPU) architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments).

Perform research and analysis with our simulation model to define the next generation of our products.

Collaborate with other research teams.

Develop Proof of Concepts using our technology, collaborating with our most sophisticated customers on state-of-the-art innovations.

We have been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As an NVIDIAN, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.



What you'll be doing:

Designing and implementing SOC level clock requirements
Developing and deploying automation flows which support SOC level design
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Own the full chip STA, analyze the timing results, verify correctness and provide budget for the different partitions.
Generate the timing constraints of complex interfaces for the STA and the P&R flow.
Be exposed and work on a variety of exciting designs (including high cell count and high frequency), resolving complex timing and congestion problems.
Help to shape the SoC clock tree, and effect the work of the different teams (Front end, DFT & BE).
Daily work involves all aspect of STA & chip design: take part in SDC generation & review, actively running & analyzing STA tools, guiding the group during chip closure process, etc'.
Taking part inflows development.
Take part in ramping up new breaking technologies.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

We are looking for a phenomenal HW Simulation team hands-on manager for the ChipSim Group.You will be leading the ChipSim growing team and take our product to next level, working closely with HW design and architect teams and gaining a deep understanding of our products and technologies.

What Youll Be Doing:

You will be responsible for leading team that learns, develop, and deliver new Networking features in simulation.

Lead definition, developing and maintaining simulation reference model infrastructure - make test suites robust, maintainable, and easily portable.

Hand-on work with Continuous integration system, regression tools, automate builds, run test suites, and analyze results.

Innovate! Bring our SDK/FW Switching products to shine in the customer's views.

Our Networking product security team is looking for an outstanding technical security researcher with hands-on experience to help us improve the security posture of our Networking software. In this role you will help reduce risk, threats, and vulnerabilities in our Networking products.

What youll be doing:

Be involved in offensive security researcher on a wide range of products.

Assist with defining and making sure software development processes meet security and coding standards.

Perform security threat modeling for our Networking products.

Design and make security architecture recommendations to satisfy security guidelines and requirements.

Mentor teams and developers, promoting guidelines on the best security practices.

Be a technical focal point across multiple development teams and provide hands-on security engineering expertise.

We are looking for a Senior Software Automation and Manual QA Engineer to join our Storage team. This position will be part of the QA team while the main goal is to test the Storage and Networking area, which enables our products to meet the industry-leading benchmarks of efficiency and quality. The ideal candidate will engage in testing of Storage and Networking drivers, be able to learn new features, execute manual and automated tests.

What you'll be doing:

Review arch design and requirements for new features.

Design and execute tests for the new features, as part of software GA releases.

Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by the R&D team, raise if not fixed.

Execute tests in different scopes: regression, performance, functional, security. report the progress of testing and provide summary reports of testing activity.

Define and build setups topologies for appropriate product coverage.

Writing automation infrastructure in multiple frameworks (Python, Perl). Developing sophisticated, stable, automation frameworks to increase efficiency, re-usability, and flexibility. Enhancements & maintenance of each framework.

Schedule test runs, publish reports and analysis with detailed and specific bug reports for failures.

We are looking for a Software Manual and Automation QA Engineer to join our Storage team. This position will be part of the QA team while the main goal is to test the Storage and Networking area, which enables our products to meet the industry-leading benchmarks of efficiency and quality. The ideal candidate will engage in testing of Storage and Networking drivers, be able to learn new features, execute manual and automated tests.

What you'll be doing:

Review arch design and requirements for new features.

Design and execute tests for the new features, as part of software GA releases.

Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by the R&D team, raise if not fixed.

Execute tests in different scopes: regression, performance, functional, security. report the progress of testing and provide summary reports of testing activity.

Define and build setups topologies for appropriate product coverage.

Writing automation infrastructure in multiple frameworks (Python, Perl).

Developing sophisticated, stable, automation frameworks to increase efficiency, re-usability, and flexibility. Enhancements & maintenance of each framework.

Schedule test runs, publish reports and analysis with detailed and specific bug reports for failures.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.


What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Plan the top level (SoC) floorplan, clock structure and verification.
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of exciting designs (including high cell count and high frequency). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.
Take part in ramping up new breaking technologies.